ENGRD 2300: Introduction to Digital Logic Design
Lab 5: Pseudorandom Number Generator
In this lab you will design, build and test a pseudorandom number generator.
The prelab for this lab is to be turned in no later than 1:25pm, Monday, October 26, 2009.
portion is to be completed during your lab section the week of October 26, 2009.
Your final lab
report is due one week following the day your lab section meets, at noon, in the drop-box for your
For this lab you may work with a partner on the prelab.
If you choose to do so, you should choose a
partner from your lab section so that you can work with the same person in lab.
You will also have to
turn in your prelab as a group in CMS.
For your convenience, a set of template files for this lab has been placed on Blackboard for you to
The top-level design file is called lab5.bdf and contains all the inputs and outputs that you will
need for this lab.
This template file defines only the required inputs and outputs; you will have to provide
the remaining design elements.
The template files also contain a template file, dualdisplay.v, for a dual
BCD seven segment display driver.
This driver takes a 4-bit input, converts it into the decimal numbers
ranging from 00 to 15, and outputs the 14 signals necessary to display this number on a pair of seven
segment displays. The template files also contain a clock divider, clk_div.v that will be used to slow the
The pseudorandom number generator that you will build for this lab operates in one of two modes.
first mode it counts normally mod 10, e.g., 0, 1, 2, 3, … 9, 0, 1, … .
In the second mode it generates a
sequence of pseudorandom numbers.
One technique for generating pseudorandom numbers is to use the
+ b (mod m)
this lab, we will set a=9, b=3 and m=16.
This formula will generate the sequence 0, 3, 14, 1, …;
repeating every 16 iterations.
The pseudorandom number generator can also be set to count either forwards or backwards.
E.g., 0, 1, 2,
3, … 9, 0, 1, … or …, 1, 0, 9, 8, 7 … in counting mode or …, 0, 3, 14, 1, … or …, 1, 14, 3, 0, … in
pseudorandom number generation mode.
For this lab, you are to design a pseudorandom number circuit using only NAND gates and
no more than
You may use NAND gates with any number of inputs. The top-level diagram of this
circuit looks like this: