lab5.tan - Classic Timing Analyzer report for lab5 Mon Oct...

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Unformatted text preview: Classic Timing Analyzer report for lab5 Mon Oct 26 23:40:01 2009 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition Q--------------------- ; Table of Contents ;--------------------- 1. Legal Notice 2. Timing Analyzer Summary 3. Timing Analyzer Settings 4. Clock Settings Summary 5. Parallel Compilation 6. Clock Setup: 'CLK50' 7. tsu 8. tco 9. th 10. Timing Analyzer Messages---------------- ; Legal Notice ;---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. a +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Summary ; +------------------------------+-------+--------------- +----------------------------------+-------------------------------------------- +------------------------------------------+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-------+--------------- +----------------------------------+-------------------------------------------- +------------------------------------------+------------+----------+--------------+ ; Worst-case tsu ; N/A ; None ; 1.724 ns ; CLK_SEL[0] ; var_clk:inst|var_clock ; -- ; CLK50 ; 0 ; ; Worst-case tco ; N/A ; None ; 11.211 ns ; Z:inst5|inst3 ; SEGLE ; CLK50 ; -- ; 0 ; ; Worst-case th ; N/A ; None ; 0.101 ns ; RDM ; Y2:inst7|inst9 ; -- ; CLK50 ; 0 ; ; Clock Setup: 'CLK50' ; N/A ; None ; 258.93 MHz ( period = 3.862 ns ) ; var_clk:inst|pclock:counter_10MHz|count[1] ; var_clk:inst| pclock:counter_1Hz|count[3] ; CLK50 ; CLK50 ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; +------------------------------+-------+--------------- +----------------------------------+-------------------------------------------- +------------------------------------------+------------+----------+--------------+ + +--------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Settings ; +--------------------------------------------------------------------- +--------------------+------+----+-------------+ ; Option ; Setting ; From ; To ; Entity Name ;...
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This note was uploaded on 12/25/2009 for the course ECE 2300 at Cornell.

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lab5.tan - Classic Timing Analyzer report for lab5 Mon Oct...

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