lab5_assignment_defaults

lab5_assignment_defaults - Copyright(C 1991-2009 Altera...

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# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2009 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II # Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition # Date created = 17:51:47 October 26, 2009 # # -------------------------------------------------------------------------- # # # Note: # # 1) Do not modify this file. This file was generated # automatically by the Quartus II software and is used # to preserve global assignments across Quartus II versions. # # -------------------------------------------------------------------------- # # set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off set_global_assignment -name SMART_RECOMPILE Off set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off set_global_assignment -name HC_OUTPUT_DIR hc_output set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On set_global_assignment -name DO_COMBINED_ANALYSIS Off set_global_assignment -name IGNORE_CLOCK_SETTINGS Off set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off set_global_assignment -name ENABLE_CLOCK_LATENCY Off set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
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lab5_assignment_defaults - Copyright(C 1991-2009 Altera...

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