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Rice_hw1

# Rice_hw1 - bit per byte as overhead A “good” resource...

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ELEC 326: Homework 1 Kartik Mohanram Due in DH 3029 by 5pm on Friday, September 11 th , 2009 Graded problems You may work together with others from the class to solve the problems on the homework, though each of you has to submit solutions that are “individually” written up. Solutions that are “near” copies of each other will not be awarded any credit. All solutions from past offerings are off limits under the honor code. 1. Analyze the following netlist (gate network) in Fig. 1 and argue that it is combinational. (Notice how quickly the truth table approach to analysis becomes a drag). Write logical expressions for all the primary outputs ( f 1 , ..., f 6 ) in terms of the primary inputs ( x 1 , ..., x 3 ). x 1 x 2 x 3 x 1 x 2 x 3 f 1 f 2 f 3 f 4 f 5 f 6 Figure 1: A cyclic circuit due to Rivest [1] 2. Derive a ballpark estimate for the number of transistors on the Montecito die. Recall the Montecito is a dual-core processor with L1, L2, and L3 caches all featuring error correction that requires 1 extra

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Unformatted text preview: bit per byte as overhead. A “good” resource for Montecito’s basic features is here: http://en.wikipedia.org/wiki/Montecito_(processor) 3. Assume that the average current drawn by a chip scales with technology, i.e., the average current decreases just as minimum feature size decreases from one generation to the next. (a) If the supply voltage V DD were held constant, what happens to the power density (power con-sumption per unit area) of a . 13 micron technology chip that is re-fabricated in . 09 micron technology? (b) What do you need to do to V DD to ensure that power density remains constant with technology scaling? (c) Comment (in four to five sentences) what supply voltage scaling does to noise immunity of the new chip. 4. Read the article Third Base provided with this homework and then prove that the optimum radix is e, the base of the natural logarithms. 1...
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