ec311hw06

ec311hw06 - 0 F = 0 0 0 1 F = A XOR B 0 1 0 F = A XNOR B 0...

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ec311hw06 10/16/2009 EC 311 – Introduction to Logic Design Fall 200 9 Homework Assignment # 6 10/16/09 Due Date: 10/27/09 (in class) Problem 1: (Verilog) Design a priority encoder module using Verilog structural description. The priority encoder has three inputs i1, i2, and i3. It has three outputs o1, o2, and o3. The relationship between the inputs and the outputs are shown in the truth table below. Write your Verilog code and show the schematic of your circuit. You can use the primitive Verilog gates described on page 3-14 of the Verilog Reference Guide (posted under the course document section on courseinfo). i1 i2 i3 o1 o2 0 0 0 0 0 1 - - 0 1 0 1 - 1 0 0 0 1 1 1 Problem 2: (Verilog) Implement in Verilog an ALU bit slice with three operation selection inputs, S2, S1, S0 that implements the following 8 functions of the two data inputs, A and B (A, B are 1 bit inputs) M = 0, Logic Mode M = 1, Arithmetic Mode S2 S1 S0 ALU Operation 0 0
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Unformatted text preview: 0 F = 0 0 0 1 F = A XOR B 0 1 0 F = A XNOR B 0 1 1 F = A OR B 1 0 0 F = A AND B 1 0 1 F = NOT A 1 1 0 F = NOT B 1 1 1 F = 1 S2 S1 S0 ALU Operation 0 0 0 F = A 0 0 1 F = B 0 1 0 F = A - B 0 1 1 F = B - A 1 0 0 F = A + B 1 0 1 F = A + 1 1 1 0 F = min(A, B) 1 1 1 F = max(A, B) Problem 3(Multiplier): Implement a 2-bit multiplier ( b a c × = , a, b are 2-bit binary vectors and c is a 4-bit binary vector) using 1 bit full adders and additional logic gates if necessary. Problem 4: Given the 4-bit magnitude comparator block, design a comparator that determines the maximum number in three 4-bit binary numbers. Connect 4-bit magnitude comparators together and using additional logic gates if necessary. The output of the circuit contains 2 bits. If the first number is the largest, the output is 01. If the second number is the largest, the output is 10. If the third number is the largest, the output is 11. Assume there are no equal numbers....
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