ec311hw07

ec311hw07 - EC 311 Introduction to Logic Design Fall 2009...

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ec311hw07 10/23/2009 EC 311 – Introduction to Logic Design Fall 200 9 Homework Assignment # 7 10/23/09 Due Date: 11/03/09 (in class) *Comment you code to receive full grades. [20 points] Problem 1 (Verilog) Give modules of Verilog Code to do the following. (Please note – use only primitive gates – i.e. AND, OR, XOR, INV for the structural questions) a) Add three 2-bit numbers behaviorally (Make sure output has enough bits) b) Add three 2-bit numbers structurally c) 1bit 4:2 Decoder behavioral d) 1bit 4:2 Decoder structural *Refer to the definition and example of structural and behavioral description in the Verilog Tutorial under Course Documents on courseinfo. [20 points] Problem2 (Verilog): Syntax and Coding The following Verilog module for a 2:1 multiplexer has some errors. Explain the errors and show how to fix them. module mux2 (result, mux1, mux2, select); input [3:0] mux1, mux2, input select; output [3:0] result; always @ (select) if (select) result=mux1; e l s e result=mux2;
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ec311hw07 - EC 311 Introduction to Logic Design Fall 2009...

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