ec311hw08 - (15) Problem 4: Using four registers, design a...

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ec311hw08 10/30/2009 EC 311 – Introduction to Logic Design Fall 2009 Homework Assignment # 8 Due Date: 11/10/09 (in class) (10) Problem 1: Using plain DFFs (with only D, Q and clk ports), MUXs and logic gates to design a 4-bit shift register with parallel load that operates according to the following function table: Shift Load Register Operation 0 0 No change 0 1 Load parallel data 1 - Shift Right (20) Problem 2: Design a 12-bit subtractor D=A-B. Assume A B. The subtractor is consisted of 3 groups of 4-bit subtractors. Use look-ahead approach to generate borrows between the groups and a. use look-ahead approach to generate borrows within a group b. use borrow-save approach within each group (20) Problem 3: Show how to connect four T flip-flops and other logic gates to create an up and down counter. Use a one-bit input S to switch between up/down counting. Assume all the flip-flops initially contain 0's.
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Unformatted text preview: (15) Problem 4: Using four registers, design a circuit that stores the previous four values seen at an 8-bit input D. The circuit should have a single 8-bit output that can be configured using two inputs s1 and s0 to output any one of the four registers. (15) Problem 5: Design a 4-bit register with 2 control inputs s1 and s0. 4 data inputs I3, I2, I1, I0, and 4 data outputs Q3, Q2, Q1 and Q0. When s1s0=00, the register clears itself to 0000. When s1s0=01, the register loads I3. ..I0. When s1s0=10, the register maintains its value. When s1s0=11, the register complements its value, so, for example, 0000 would become 1111, and 1010 would become 0101. (20) Problem 6: Design a counter according to the following transition diagram using minimum number of DFFs and MUXs. Do not use any logic gates other than inverters. 4 2 6...
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This note was uploaded on 12/29/2009 for the course ENG EC 311 taught by Professor Karpovsky during the Fall '09 term at BU.

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