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PracticeProblems2

PracticeProblems2 - Chapter 2 Operational Amplifiers ° The...

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Unformatted text preview: Chapter 2 Operational Amplifiers ° The following three problems refer to the circuit shown below. Assume the op-amp to be ideal. R3 = 15 k9 ° vOUT VIN - i VEE R2 = 6 kfl 2.1 For the op-amp circuit shown above, find and evaluate an expression for VDUT as a function of VIN. [/w% 2.2 Consider the op-amp circuit shown above. Find the input resistance ?',} seen between the VIN terminal and ground. 2.3 If the input voltage to the op-amp circuit shown above becomes too large, the op-amp will saturate. For what values of VIN will this condition occur if VCC = 10~V and VEE = -15 V? ‘ 0 The following four problems refer to the op-amp circuit shown below. The op-amp is ideal. R3 = so kn ' VOUT VEE 2.4 Consider the op—amp circuit shown above. Find and evaluate an /”3 expression for VOUT as a function of VIN. 2.5 Consider the op—amp circuit shown above. Find the input resistance seen between the VIN terminal and ground. 2.6 If the input voltage to the op—amp circuit shown above becomes too large, the op—amp will saturate. For what values of VIN will this condition occur if VCC = 15 V and VEE = —12 V? 2.7 Suppose that the input voltage to the circuit shown above is large enough to drive the op—amp into saturation. Find an expression for the input current iIN as a function of the input voltage VIN under saturation conditions. 2.8 Design an op—amp circuit that has a voltage gain of 2 and an input resistance of 100 kn. 2.9 Design an op—amp circuit that has a voltage gain of -2 and an infinite input resistance. 2.10 The following circuit contains an ideal op-amp. Find an expression for VOUT as a function of VIN. 3R1 2.11 Consider the circuit shown above. Find the input resistance seen between the VIN terminal and ground. 2.12 Consider the op-amp circuit shown below. 3) Find VDUT as a function of Va and Vb- b) Find the input resistance to ground seen at each input terminal. Each input resistance should be evaluated with the remaining input source set to zero. 2.13 Repeat the previous problem for the op—amp circuit shown below. 2.14 Assume the op—amp in the circuit shown below to be ideal. Find an expression for VOUT as a function of VIN. The voltage Vref has a constant value. ‘ 3’ “my 2.15 2.16 2.17 ' 2.18 2.19 For the circuit shown below,' find an expression for VUUT as a function of v1 and v2. 10 kfl 200 kfl Design an op-amp circuit with two inputs such that VOUT = 2(v1 - v2). The input resistances to ground at v1 and v2 are to be infinite. Design an op—amp circuit with two inputs such that VOUT = 2V1 — v2. The input resistances to ground at v1 and v2 are to be infinite. Find VOUT in the circuit shown below. The op-amp is ideal. A loo-Hz triangular waveform of :IO-V peak is applied to the comparator circuit shown below. Sketch VUUT as a function of time if VCC = 15 V and VEE = —15 V. 2.20 2.21 2.22 2.23 2.24 2.25 In the circuit shown below, v1 is a 1—kHz, lO—V peak triangular waveform and v2 is a iS-V square wave with half the period. Both input waveforms paSS through zero at the same time. Plot VDUT as a function of time if VCC = 15 V and VEE = ~15 V. Assume the op—amp to be ideal. Vcc T v1 vOUT v2 l A comparator circuit is fed from a VIN source connected to the v+ terminal. A constant 2—V reference Vref is connected to v-. Sketch the Circuit’s transfer characteristic if Vcc = 10 V; VEE = —10 V. VEE Repeat Prob. 2.21 if VIN is connected to v- and Vref to v+. Repeat Prob. 2.21 if VCC = 15 V and VEE = -12 V. A 5—V peak triangular voltage with a period of 20 ms, depicted on the axes shown below, is applied to an ideal op—amp integrator. Plot VUUT as a function of time if Vcc = 15 V and VEE = —15 V. The capacitor has zero initial charge. C=5/1F vIN VIN 5 V t (ms) 10 2O -5 V Plot the output of the integrator shown below if VIN is a symmetri- cal square wave with an amplitude of 5 V and a period of 1 ms. The output is initially zero. The square-wave is turned on as it makes its initial transition from O to 5 V. C 5 pF VIN VIN(t) VUUT "' _. l VEE = —12 V O > t - —5 V Q- 1 ms ~9| 2.26 Repeat Prob. 2.25 if the input consists. of a 5-V peak square wave superimposed on a constant dc component of 0.1 V. 2.27 Repeat Prob. 2.25 if the the input consists of a 5-V peak square wave superimposed on a constant dc component of —0.2 V. 2.28 A Schmitt trigger constructed with a feedback ratio of 0.2 is driven by a 3-V peak sinusoid. Plot the output versus time of VCC = 'VEE = 10 V. 2.29 Repeat Prob. 2.28 for a feedback ratio of 0.4. 2.30 The input voltage depicted below is applied to a Schmitt trigger for which R1 = R2 = 10 RH and VCC = ‘VEE = 12 V. Plot VQUT as a function of time. VIN (V) The power extracted from the With an additional 1 Mn resistor circuit will multiply v+ by the non— connected, the current out of the inverting gain, so that the output resistive circuit becomes becomes 10 V R3 + R1 19 kn TITVETTTTTTVfiiz 20 pA VOUT = ——§;—-VIN = 3 kfl VIN = 6-3VIN 20 pA ' Resistive {0 V [:::::] If the op—amp is ideal, the C'rcglt ' current into the v4. terminal will be zero. This current is identical to 'For the general Thevenin equivalent the iIN flowing through R2, hence iIN shown below, v = VTh — iRTh. = O and Rin = w. RTh i+ [:::::] An ideal op-amp saturates when VUUT reaches VCC or VEE- As shown in + vTh V . . _ Prob. 2.1, the c1rcuut has voltage gain Av = 6.3, hence VOUT will equal , . VCC for Applying the known data results In: V C 10 V 12 V = VTh — (12 pA)RTh, and VIN 2 -A_ = -—- a 1.6 V 10 v = vTh — (20 pA)RTh. v 6'3 Simultaneous solution of these equa- Similarly, the op-amp wull saturate tions yields vTh = 15 v; RTh = 250 kn at VEE for VEE -15 V VIN S -— = ~——- 2 -2.4 V Av 6.3 supply is equal to (10 V)(2 mA) = 20 mW. The power dissipated in the load Since the op-amp is ideal, the is (5 V)2/(10 k0) = 2-5 mW. (Alterna— current into the v+ terminal will be tively, (5 V)(0-5 mA) = 2-5 mW). The zero. As a result, no current flows power dissipated in the circuit is through R2, and the voltage drop equal to the difference: 20 mW ‘ 2-5 across R2 becomes zero. With v+ held mW = 17-5 mW at ground potential by R2, the cir- _MW_, cuit functions as a simple inverting .amplifier with Chapter 2 ‘ . “R3 _30 kn v _ - v = v = —7.5 v . . OUT R1 IN 4 kfl IN IN If the op—amp IS Ideal, the current into the v+ terminal will be AVD 0.68 V _ 0.70 V o zero,_and no voltage drop Wlll occur KT— = —-———E6—SE—~——- = -1.5 mV/ C across R2. The voltage at v+ will - thus equal VIN. The remaining 78 associated with lIN can be represent— /, The Input resustance ls defined, ed in the following way: ‘ ” as VIN/lIN: where lIN is the current flowing into R1. As noted in Prob. R3 = 30 k0 v- + V that the op—amp is not driven into _1;f CC saturation by an excessively large _ 2.4, the v+ terminal is held at VIN R1 = 4 k“ ground potential by R2. Assuming E lIN -£~ VIN, the v- terminal will also be forced to ground potential. by From this circuit, it follows that _negative feed-back. The input VIN _ VCC current iIN thus becomes simply lIN = ---—-—- VIN/R1, so that R1 + R3 A VIN VIN where VIN is negative and lIN will be Rin = 7;; = :Efiifi; = R1 = 4 k0 negative also (i.e. current will flow 6 T of R1). Similarly, for large pos— itive VIN: VIN - VEE Q i l . E An Ideal Op-amp saturates when 'IN - R1 + R3 VDUT reaches Vcc or VEE- As shown in ‘ where V is a ne ative volta e. For E Prob. 2.4, the circuit has a voltage EE 9 g , . this latter case, current will flow M». , gain of Av = -7.5, hence VOUT Wlll into R a ,% equal VCC for 1' ”’ v 15 v VIN S -§£ = -—- = -2 V V ”7‘5 The specifications can be met Similarly, the op—amp Will saturate by several circuit configurations. at VEE for Two possibilities are given below. VIN _ Egg = :33_V= 1.6 V The power supply connections are not Av '7-5 shown. Note that the circuit is an inverting amplifier, hence VUUT reaches its positive saturation value for nega- VIN ° tive VIN and its negative saturation 100 kfl value for positive VIN. When the op-amp saturates, neg— ative feedback will no longer be capable of forcing v- to the same voltage as v+. The condition i_ = 0 will still be true, however. For E X saturation at VUUT = Vcc (i.e., for ““T large negative VIN), the circuit 79 The op—amp is shown below with VIN connected to the inverting portion of the circuit (R2 connected to ground): Since the current into the v+ termi— nal is zero, the voltage drop across the parallel resistance R2||2R2 is The required specifications can 3'50 zero. Thus VDUT f°" this subcir- cuit becomes (-3R1/R1)VIN = '3VIN- be met by buffering an inverting am- , h , h plifier (R2 = 2R1) with a unity-gain The op—amp is next 5 own "It YIN voltage follower The resistor val- connected to the noninverting portion ./" . - - i E , ues shown below produce a gain of -2 Of the Circuit (R1 connected .to ground): but are otherwise arbitrary. From the voltage divider relation, the voltage applied to the v+ terminal becomes 2R2 2 v = v —--——- = - VIN The circuit has the topology + IN R2 + 2R2 3 ‘ f/“3 of both an inverting and a This voltage is multiplied by the K, a noninverting amplifier. The output noninverting gain (3R1 + R1)/R1 = 4. can be found _using superposition. 8O The second component of VOUT thus becomes 4(2/8)VIN = (8/3)VIN' The total iIN becomes the sum of i1 Adding together the two superimposed and 32: VIN VIN Components of VOUT yields the total IIN = 3E“ + EE— output: 1 2 8 ‘VIN The input resistance thus becomes VOUT = '3VIN + EVIN = -g- VIN 1 1 -1 Rin = — = 3[——— + ————] = 3(R1IIR2) iIN R1 R2 The input resistance can be a) A summation amplifier is determined by finding the ratio VIN/iIN. The current lIN has two formed by resistors RA: RBI and R25 components i1 and i2, as shown below. RC has no effect on VDUT: since the ' current through it is zero. The output thus becomes R2 R VOUT = - -va - “”Vb = -2va - Vb RA RB b) The v+ terminal is held at ground potential by Rc, and v_ is forced to the same voltage as v+ by the nega- tive feedback. Hence the v- terminal will also be held at ground poten- tial. The input resistances at the two input terminals are defined as Va/lRA and Vb/lRB: where lRA and lRB are the currents into RA and RB, re- spectively. With v_ = O, the input resistances become simply RA and RB. Given that i4. = 0, it follows that VIN VIN i2 = -——————— - ——— The voltage divider relation can be - 2.13 a) Resnstors R1 and R2 form a l' d t R d 2R b ' = O. app '6 o 2 an 2 ecause l+ noninverting amplifier that multi- Hence via volta e division ’ 3R 2 ’ plies v+ by a gain of 2. The voltage ____Z___ = - VIN at the v+ terminal can be found by 2R2 + R2 3 forming the Thevenin equivalent 0f If VIN is small enough SUCh that VDUT RA, RB, RC, and the input sources: remains within the op—amp’s satura— tion limits, then v- will be equal to v+ (linear op-amp operation). With v- at the same voltage value as v+, the current i1, which is set by the V... = VIN (pf: voltage drop across R1, becomesflr_v 7 ;”' VIN - V- VIN[ 2 l VIN |1=—-————=-—— 1--— =--- »1 R1 R1 3 3R1 ‘ 81 vTh where RTh = RAllRBllRC = 5 k0 and R R R R -VTh=Va BllC ”b AllC RA + RBHRc RB + MW 10 k0 6.7 kn = ya ——————-———-— + vb -+—----‘—— 10 k0 + 10 k0 20 kfl + 6.7 kfl va vb ‘ =-—+-—— 2 4 With an inverting gain of 2, the output becomes VUUT = va + Vb/2- b) Since the v+ terminal appears as an open circuit to RA, RB, and RC, resistors R1 and R2 do not affect the input resistances seen by Va and Vb- The latter are found by alternately setting Va and Vb to ground, yielding Rina = RA + RBllRC = 10 kn + 10 k0 = 20 k0; Rinb = R3 + RAllRC = 20 kfl + 6.7 k0 = 26.7 kn. Use superposition to find the output. With Vref temporarily set to zero (set to a short circuit), the circuit becomes a noninverting ampli- fier with a gain of (R2 + R3)/R2. Note that the current flowing through R1 is zero (i+ = 0), hence R1 does not affect the noninverting gain. With VIN temporarily set to zero, the circuit becomes an inverting amplifier with a gain of -R3/R2. Once again, R1 has no effect on the inverting gain. The total output, position, becomes given by super- I I 82 ' Represent the network connected to the v+ terminal by its Thevenin equivalent circuit: 10 k0 ’division and v2 set alter— where, via voltage superposition (v1 and nately to zero), 2 1 vTh=-3-V1+§V2 The Thevenin resistance is given by RTh = (100 kfl)||(200 kfl) = 66.7 kn The op-amp circuit multiplies VTh by a noninverting gain of 11. Note that RTh has no effect on the gain of the circuit since the current through it is zero (i+ = O for an ideal op—amp). With a noninverting gain of 11 and the computed VTh: the output becomes 22 11 VOUT = —'3' v1 + "3-" v2 = 7.3v1 + 3.7V2 The following circuit will provide the desired function: vOUT ,The followers A1 and A2 provide voltages vx = v2 and VY = v1 to the difference amplifier A3, for which R2 R2 + R1 R2 V v = --—-~ --*-- - *— UUT R1+R2 R1 Y RIVX voltage divider noninverting coefficient gain The above expression reduces to R VOUT = R—: (VY - Vx) = 2(V1 - V2) if R2 = 2R1 6.9. R2 = 20 kn; R1 = 10 kfl. To the extent that the op—amps are ideal, the two follower stages also provide infinite input resistances to ground at the v1 and v2 terminals, as specified. The solution to this problem has the same basic form as that of the previous problem. In this case the resistor R2 at the v+ terminal of A3 is omitted, thus eliminating the voltage divider coefficient from the expression for VUUT- The latter becomes . R2 + R1 R2 v = -——-~* v - ~w v OUT } R1 Y R1 X 83 where VY = v1 and vx = v2. R1, VOUT becomes 2V1 - v2. If R2 = For linear operation, v+ = v_, hence the drop across R2 will be zero and the current through it zero as well. Any current flowing through R1 or R3 must flew through R2, since i+ and i- are zero. Hence the currents through R1 and R3 must also be zero. These three resistors may thus be ig— nored (no voltage drop occurs across them), reducing the circuit to the following form: vIN ' ' vOUT R5 R4 We recognize this circuit as a non- inverting amplifier with output . R5 + R4 vOUT = R4 VIN The output of the comparator will satUrate at VCC when the op-amp' voltage (v+ - v_) is positive. Simi— larly, VDUT will saturate at VEE when the voltage (v+ - v_) is negative. The v; terminal of the op-amp is fixed at 5 V, hence (v+ — v_) will be positive for VIN ( 5 V; conversely,'f '” (v+ - v_) will be negative for VIN ) 5 V. - The transfer characteristic of the comparator, which summarizes this relationship, is shown below: VOUT (V) 15 VIN (V) If VIN is a 100-Hz, 10-V peak trian- gular waveform, the output will switch between VCC and VEE when the input passes through 5 V: The status of the output of the comparator is determined by the instantaneous value of (v+ - v-). Specifically, VUUT will saturate at VCC when (v+ — v-) is positive; VOUT The output will saturate at will saturate at VEE when (v+ - v-) V = 15 V when (v+ - v_) is positive is negative. _ . (S: ) v2). Conversely, the output For the circu:t described, .v7 = will saturate at VEE = -15 V when (v+ 2 V, hence (v+ - v-) Will be pos:tive - v-) is negative (v1 < v2). The re- (VDUT = 10 V) for. VIN > 2 'V' lationship between v1 and v2 at each Similarly, (V+ ' V-) wull be "egat've point in time thus determines VOUT: (VUUT = ‘10 V) for vIN < 2 V- 84 vOUT 10 V VIN 2 V -10 V The status of the output is again determined by the instantaneous value of (v+ - v_). Specifically, VDUT will saturate at VCC when (v+ - v-) is positive; VOUT will saturate at VEE when (v+ - v-) is negative. In this case, v+ = 2 V, hence (v+ - v-) will be negative (VDUT = VEE = -10 V) for VIN > 2 V. Similarly, (v+ - v-) will be positive (VUUT = VCC = 10 V) for VIN < 2 V. vOUT 10 V VIN 2 V -10 V m The status of the output will 85 again be determined by the instan~ taneous value of (v+ - v-), i.e. VOUT will saturate at VCC when (v+ — v-) is positive; VOUT' will saturate at VEE when (v+ - v_) is negative. In this case, VEE and VCC have different magnitudes, hence the transfer characteristic will be an asymmetrical version of that found in Prob. 2.21. The transition voltage, determined by the input conditions, will remain at 2 V. VOUT 15 V vIN 2 V -12 V This circuit is a simple integrator with output given by 1 t VOUT = — E5 Io VIN dt Over the interval 0 < t < 5 ms, VIN can be expressed as VIN = at, where a = 1 V/ms and t is in milliseconds. For the R and C values shown, RC = (10 kfl)(5 pF) = 50 ms. Thus the out- put becomes 1 t at2 VOUT = - RE [oat dt = - EEE _ (1 V/ms) 2 _ _ t2 ' - 2(50 ms) ' 100 ms2/v where t is in milliseconds. This expression describes a parabolic vol- tage waveform whose slope increases in magnitude with time. Its value at ‘ \«m/ t = 5 ms (the positive peak of VIN) is -(5 ms)2/(1oo ms2/V)= -o.25 v. Over the next 5—ms time interval, during which VIN is positive but returns to zero, VOUT will continue increasing negatively, but its slope will become more shallow as time progresses. By symmetry, the waveform over this second time interval will be the vertical mirror- image of the waveform obtained during the first 5 ms. At t = 10 ms, VOUT will reach the value ~0.5 V. Over the next 10 ms, during which time VIN becomes negative, VOUT will begin to decrease, reaching zero at t = 20 ms. The waveform over this time interval will be the horizontal mirror image of the waveform obtained during the first 10 ms. . V0UT(V) [::::::] The output of the integrator is given by -1 t VOUT = EE_ Io VIN dt The output is initially zero and the square wave begins with a zero to 5 V transition. While VIN remains at a constant value (either 5 V or -5 V), the integrator output will become a ramp that progresses as *(5 V) t W = *(0.1 V/ms) t 86 where t is in milliseconds and RC = (10 kfl)(5 fiF) 50 ms. During the first 0.5 ms of VIN (VIN = 5 V), the output will ramp down to the value (-O.1 V/ms)(0.5 ms) = -50 mV. During the next 0.5 ms of VIN (VIN = -5 V), the output will ramp up a total of (0.1 V/ms)(0.5 ms) = 50 mV, back to zero. At no time will the output reach its saturation limits. Here is a plot of VOUT versus time: A vOUT (mV) The dc component of VIN will introduce an additional voltage com- ponent to VOUT. The latter will consist of a ramp that progresses as - 0.1 V t --£-—-2--= ~(2 mV/ms) t (10 kfl)(5 pF) where t is in milliseconds. This constantly decreasing ramp will be superimposed on the triangular output signal found in Prob. 2.25. After 6 s, the new ramp component will reach the value -12 V, causing VOUT to saturate at VEE- (The actual time at which VOUT first saturates may be slightly different due to the 50 mV triangular signal component of vuuT; the output will first reach satura—. tion when the total VOUT reaches VEE). Here is a plot that depicts VOUT as a function of time: VIN , A 3-V peak sinusoid (VIN = 3 sinwt V) See the solution to Prob. will reach 2 V at wt 2 42°. Similar— 2.25. In this case, the constant ly, it will reach -2 V at wt = 318°. ramp component added t0 vOUT “iii v Here is a plot of VOUT versus time progress at the rate that reflects these transition angles —(-0.2 V) t of VIN: (10 km) (5 ,uF) = (4 '"V/ms) t where t is again in milliseconds. ‘ VOUT (V) For this positively increasing ramp, VOUT will saturate when it reaches VCC = 12 V, which will occur at 3 s: VOUT (V) 5 s t . ' i For a feedback ratio of 0.4 and VCC = ‘VEE = 10 V, the transition voltages of the Schmitt trigger For the saturation values’VCC become 14 V. A 3-V peak sinusoidal ' = 10 V and vEE = ‘10 V, and f°r a input will never reach these feedback ratio of 0.2, the transition transition values, hence VOUT will voltages of the Schmitt trigger will not change with time. be equal to t(0.2)(10 V) = 12 V. Here is the Circuit’s transfer characteristic: 87 ' Graphical method: Plot the load line of VTh and RTh For the specified circuit con- over the v-i characteristic of the ditions, the Schmitt trigger transi- square—law device: tion voltages will be :6 V. The is (mA) output will change from VCC = 12 V to ‘ VEE ...
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