ceg3156Assignment3Solutions.pdf - CEG 3156 Computer Systems...

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CEG 3156: Computer Systems Design (Winter 2018) Prof. Rami Abielmona Possible Solutions to Assignment #3: Processor Efficiency Schemes 23 February, 2018 Question I This question deals with multi-cycle processor implementation schemes. Many solutions are possible. In all of them, a multiplexor will be needed as well as a new control signal (e.g., RegRead) to select which register is going to be read (i.e., using IR[25-11] or IR[20-16] ). One simple solution is simply to add a write signal to A and break up state 1 into two states, in which A and B are read. It is possible to avoid adding the write signal to A if B is read first. Then A is read and RegRead is held stable (because A always writes). Alternatively, you could decide to read A first because it may be needed to calculate an address. You could then postpone reading B until state 2 and avoid adding an extra cycle for the load and store instructions. An extra cycle would be needed for the branch and R-type instructions.

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