ch4_amplifier_09-16

ch4_amplifier_09-16 - Power Conversion Efficiency (ηC) PL...

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Unformatted text preview: Power Conversion Efficiency (ηC) PL Ave Power delivered to the load = Power drawn from the su pplies PSupply Psupply = 2 VCCIQ (constant) Assume the biasing current IR is small 1 PL max 2 [VCC − VCE ( sat ) ]I Q 1 VCE ( sat ) η c max = = = 1 − PSupply VCC 2VCC I Q 4 For VCE(sat) « VCC, ηCmax ≈ 25% (Not Good!) Also, standby Power = 2VCCIQ (very large!) ηC = Instantaneous Power of Q1 VCC = fixed voltage C vi Q1 B E IQ Vce1 2VCC VCC 0 2IQ IQ 0 t Pc1 t Ice1 Ice1 vo RL When Vce1 increases, Ve decreases, i.e. VO decreases ⇒ Ice1 decreases (because IRL = Ice1-IQ) Power dissipated in the active device Q1 PC1 = Vce1Ice1 For maximum signal swing with RL = RL3 PC1 = Vce (1 + sinωt) IQ(1 − sinωt) = VCCIQ (1 − sin2ωt) VCC I Q = (1 + cos2ωt) 2 ∴PC1max = VCCIQ Note: To design an output stage, make sure VCCIQ is less than the rated power of a transistor. E.g. Prated = 1W, VCC = 10V ⇒ IQ < 100mA Small Signal Properties VCC I Q r + RS where RS is the source resistance RO = π 2 β +1 v RL 0 AV = o = . r + RS vi RL + π β +1 Since rπ depends on the quiescent current IQ, Ro and Av are IQ dependent. t Note: 1. EF Output Stage — no voltage gain but high power gain. 2. Vomax = VCC – VCE(sat) for any vI. If vI is limited to VCC, Vomax = VCC – VBE1. Disadvantage in Class A — large power dissipation even in standby mode. Solve the problem by using 2 active devices (1 for each ½ cycle). Last updated: 22-Nov-03 9 Class B (PUSH-PULL) Output Stage VCC Q1 vi Q2 −VCC Note: vo RL Transfer Char. VCC − VCE2(sat) −VBE(on) vo Q1 saturated Q1 ON, Q2 OFF 0 Q2 ON, Q1 OFF Q2 saturated VBE(on) −VCC + |VCE2(sat)| Slope =1 vi deadband 1. No-load current is zero (Both Q1 & Q2 are OFF). 2. Deadband of ~2VBE(on) lead to crossover distortion. vo vi VBE(on) t t 3. Bad for small signals. Class AB Output stage VCC IQ Q1 Q3 Q4 vi Q2 −VCC vo RL Transfer Char. vo VCC + VCE1(sat) −VBE(on) −VCC + |VCE2(sat)| 0 vi Note: 1. No dead band. 2. Small quiescent current (IQ is only used for making sure Q3 & Q4 are ON). 3. Output biasing current depends on the area ratio of Q1, Q2, Q3 and Q4. V Since I C = I S exp BE , if Q1& Q2 is 10 times larger, Ioutput = 10 IQ. V T Last updated: 22-Nov-03 10 Power Output and Efficiency ˆ2 1 VO PL = 2 RL VO VO ^ Power supply current (average value) 1 1 Tˆ I S1 = ∫ T I C1 (t )dt = 0 0 I O sin tdt 2π ∫ T ˆ ˆ I 1ˆ 1 VO π = O [− cos t ]0 = I O = 2π π π RL IS2 = IS1 = Isup ˆ V 2 Psupply = 2 VCCIsup = VCC O π RL ˆ2 1 VO ˆ P 2 RL π VO ⇒ ηC = L = = Psu pply 2 VCC ˆ 4 VCC VO π RL ˆ Since VOm = VCC – VCE(sat) ⇒ PL 0 t IC1 ˆ ˆV IO = O RL 0 t IC2 0 t ˆ V ˆ − IO = − O RL ˆ Now, ηC is independent of RL and proportional to VO . max = 2 1 [VCC − VCE ( sat ) ] or η C RL 2 max = π VCC − VCE ( sat ) 4 VCC For VCE(sat) « VCC , ηCmax ≈ 78.5% Note: standby power ≈ 0 (IQ can be biased to a very small value) Instantaneous Power of Q1 and Q2 PC = VceIC = (VCC−VO) IC = (VCC – ICRL) IC = ICVCC – IC2RL Differential the above equation show that PC reaches its peak value at dPC V =VCC – 2ICR L= 0 ⇒ IC = CC dI C 2RL ∴ PC 1 VCC max 4 RL E.g. VCC = 9 V, RL = 8 Ω. 2 1 VCC 1 92 PC max = = = 2.53W 4 RL 48 = PC max = 2 1 VO 1 (VCC − VCE ( sat ) ) = 2 RL 2 RL ^2 Graphical method V V − VCE IC = IO = O = CC RL 2RL IC = − iC VCC RL VCE VCC + RL RL Load line Slope = − 2 1 RL Peak device dissipation Load line VCE VCE(sat) VCC 2Vce–VCE(sat) VCC 2 0 1 (9 − 0.3) 2 = = 4.73W 2 8 Last updated: 22-Nov-03 11 Practical Example: 741 OpAmp (Class AB) VCC = 15V Bias Q13B 0.22mA Q19 0.68mA V1 vi Q17 −VCC = −15V Output bias current in Q14 and Q20 depends on the effective area ratio between diode Q18, Q19 and output devices Q14, Q20. VO = −VCC + VCE17(sat) – Vbe23 – Vbe20 = −VCC + 0.2 + 0.6 + 0.6 = −VCC + 1.4V = −13.6V VO+ = VCC − VCE13(sat) – Vbe14 = VCC – 0.2 − 0.6 = VCC − 0.8V = 14.2V Q13A 0.17mA Q14 RL + vo − Q18 V2 Q23 Q20 When Q17 is cutoff, max current is limited by IC13A. ∴ Max. limited positive current IO = β14 × 0.22mA When Q17 is active, there is no max. current limit. ∴ No max. limit for negative output current. Note: No deadband & good linearity. vo 14.2V 0.645 −13.6V vi Detail schematic of Q18 and Q19 − Output devices Q14 & Q20 are typically 4 times and 2 times larger than the standard devices to handle high current. − Vbe drop of Q14 & Q20 is smaller than the standard devices. − Most current is handled by Q18 and thus Q19 has a smaller current and Vbe drop. VCC Bias Q13B 0.22mA Q19 0.6/40k =15µA V1 R10= 40kΩ Q23 −VCC 0.17mA (@VO=0) Q14 ×4 + RL v − 205µA Q18 Q20 ×2 o Vbe19 +Vbe18 = Vbe14 + |Vbe20| I I I I VT ln C19 + VT ln C18 = VT ln C14 + VT ln C 20 I S19 I S18 I S14 I S 20 I C19 I C18 I = C14 I S19 I S18 I S 14 I S 20 ⇒ I C14 = I C19I C18 I S 14 I S 20 = − I C 20 I S 19 I S18 2 OR R2 + (1+R2/R1)Vbe18 R1 − Last updated: 22-Nov-03 12 Multistage Amplifier VCC = V4 + V21 − V2 V22 V3 V5 R7 Step 1: Find DC Biasing condition (Assume β = ∞) 15 − 0.7 IC9 = (0 + VCC − VBE(on))/R7 = = 0.5 mA 28.6k IC3 = IC9 = 0.5 mA and IC6 = 4IC9 = 2 mA IC1 = IC2 = ½ IC3 = 0.25 mA and IC4 = IC5 = ½ IC6 = 1 mA V3 = VCC – IC5R3 = 15 − (1m)(3k) = 12 V V4 = V3 + |VBE(on)7| = 12 + 0.7 = 12.7 V V − V4 15 − 12.7 IC7 = CC = = 1 mA R4 2.3k V5 = -VCC + IC7R5 = −15 + 1m(15.7k) = 0.7 V VO = V5 – VBE(on)8 = 0.7 − 0.7 = 0 V VO − VEE 0 + 15 = = 5 mA IC8 = R6 3k V21 = V22 = VCC – IC1R1 = 15 − 0.25m(20k) = 10 V −VCC = Common-mode input voltage range: Max: Vicm+ = V21 – VCE(sat)1 + VBE(on)1 = 10 − 0.3 + 0.7 = 10.4 V Min: Vicm+ = −VCC + VCE(sat)3 + VBE(on)1 = −15 + 0.3 + 0.7 = −14.0 V Output range: Max: VOmax = V4 – VCE(sat)7 – VBE(on)8 = 12.7 – 0.3 -0.7 = 11.7 V Min: VOmin = −15 V when IC4 is very small. Last updated: 22-Nov-03 13 Find AC performance (Assume β=100, VT = 25mV) Step2: g v A1= 2 = m1 [( R1 + R2 ) //(rπ 4 + rπ 5 ) //(ro1 + ro 2 )] = g m1 ( R1 // rπ 4 // ro1 ) ≈ g m1 ( R1 // rπ 4 ) vid 2 βV 100 ⋅ 25m β I 0.25m g m1 = C1 = = 0.01 A / V & rπ 4 = = T= = 2.5kΩ VT 25m g m4 I C 4 1m ∴ A1 = 0.01(20k//2.5k) = 22.22 V/V v 1 1 A2 = 3 = − gm4{ro5//R3//[rπ7 + (β7 +1)R4]} ≈ − gm4{ R3//[rπ7 + (β7 +1)R4]} 2 v2 2 βV 100 ⋅ 25m I 1m gm4 = C 4 = = 0.04 A / V & rπ 7 = T = = 2.5kΩ VT 25m IC7 1m 1 ∴ A2 = − (0.04)[3k//2.5k + (101) 2.3k] = −59.24 V/V 2 v5 g m 7 {R5 // [rπ 8 + ( β 8 + 1) R6 ] // ro 7 [1 + g m 7 (rπ 7 // R4 ]} =− A3 = v3 1 + g m 7 R4 βV 100 ⋅ 25m 1m I = 0.04 A / V & rπ 8 = T = = 500Ω gm7 = C 7 = 25m VT IC8 5m 0.04[15.7k // 0.5k + (101)3k ] = −6.421 V/V ∴ A3 = − 1 + 0.04(2.3k ) V αV v R6 α 25m A4 = o = = T≈ T= = 5Ω & re8 = v5 R6 + re8 g m8 I C8 I C8 5m 3k = 0.9983 V/V ∴ A4 = 3k + 5 Differential voltage gain Ad = A1A2A3A4 = (22.2)( −59.24)( −6.421)(0.9983) = 8438 V/V = 20log(8438) = 78.5dB Common-mode voltage gain Acm = A1cmA2cmA3A4 v g {R //[ r + ( β 4 + 1)2ro 6 ] // ro 2 [1 + g m 2 (rπ 2 // 2ro 3 ]} − g m1 R1 where A1cm = 22 cm = − m1 1 π 4 ≈ v1cm 1 + g m1 (2ro 3 ) 1 + 2 g m1ro 3 V 100 0.01(20k ) ro 3 = A = = 200kΩ ⇒ A1cm = − ≈ −0.05 1 + 0.01(2)(200k ) I C 3 0.5m v3 g {R //[r + ( β 7 + 1) R4 ] − 0.04[3k // 234.8k ] ≈ − m5 3 π 7 = = −0.02961 V/V and A2cm = v22 cm 1 + g m 5 (2rO 6 ) 1 + 0.04(2)(50k ) ∴ Acm = (−0.05)( −0.0296)( −6.421)(0.9983) = −9.487×10−3 V/V CMRR = Ad 8438 = 8.89×105 = 119dB = −3 Acm 9.487 * 10 βV 100 ⋅ 25m = 20 kΩ Rin = rπ 8 = 2 T = 2 ⋅ 0.25m I C1 R 15.7k Ro = R6 //( re8 + 5 ) = 3k //(5 + ) = 152.3Ω β8 + 1 101 Last updated: 22-Nov-03 14 More on Differential Pairs Emitter Degeneration Ad = − g m {RC // rO [1 + g m (rπ // R E ]} 1 + g m RE RC − vo + + vid − RE RC For single-ended output, g {R // r [1 + g m [rπ //( RE + 2 REE )]]} Acm = − m C O 1 + g m ( RE + 2 REE ) For differential output, Acm = 0 Cascade rπ 3 Ad = g m 3 ( RC // rO 3 ) rπ 3 + re1 RE +vid/2 Q1 RC Q3 − vo + RC Q4 Q2 −vid/2 Note that re1 may not necessary « rπ3. It depends on the values of IEE1 & IEE2. IEE1 = IEE2, Ad = g m3 ( RC // rO 3 ) I 1 IEE1 = 0, I C1 ≈ C 2 , Rin ↑ by ≈β times, Ad = g m 3 ( RC // rO 3 ) 2 β Cascode Q7 RC Q3 VBias Q1 + vi − Q2 Q1 + vi − Ad = gm1[RC//(β+1)ro] − vo + Q4 Q3 RC Q5 IEE2 IEE1 IEE2 Q8 Q6 vo Q4 VBias Q2 Ad ≈ gm1[βro4//βro6] Last updated: 22-Nov-03 15 More Example: 741 Op Amp ii βii v4 ½gmvid v2 v3 RL Note: 1. R3 is used to increase the collector current of Q7 and prevent the β value of Q7 to be too small 2. R6, R7, Q15, Q21, R11, Q24 and Q22 are used for overload protection circuitry. It prevents the transistors to burn-out when the output is shorted to ground. Q16 is used to increase the gain of the 1st stage. Q23 is used to increase the gain of the 2nd stage. Small Signal Analysis Rid = [rπ1+(β1+1)re3]×2 = 4 rπ1 (Q IC1 = IC3) v v v g ∴ ii = id = id & β1ii = id β1 = m vid Rin 4rπ 1 4rπ 1 4 ∴ β IC v2 g m1 = {ro6[1+gm6(rπ6//R2)] // ro4[1+gm4(rπ4//re2)] // {rπ16+(β16+1){R9//[rπ14+(β17+1)R8]}}} vid 2 v3 R9 //[rπ 7 + ( β17 + 1) R8 ] = ≈1 v2 {R9 //[rπ 7 + ( β17 + 1) R8 ]} + re16 1 v4 = { ro13B // {ro17[1+gm17(rπ17//R8)]} // {rπ3+(β23+1)[rπ20+(β20+1)(R7+RL)]} } for VO < 0 v3 1 + g m17 R8 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · // {rπ3+(β23+1)[re18+re19+rπ14+(β14+1)(R6 +RL)]} for VO > 0 vo ≈1 v4 Ro = R7 + re20+ 1 β 20 + 1 {re23 + 1 β 23 + 1 {ro13B // ro17[1+gm17(rπ17//R8)]}} for VO < 0 Last updated: 22-Nov-03 16 ...
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This note was uploaded on 01/05/2010 for the course EENG 202 taught by Professor P.mok during the Spring '03 term at Arizona.

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