ch2_MOS_01-14 - ELEC202 – Electronic Circuits II MOS...

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Unformatted text preview: ELEC202 – Electronic Circuits II MOS Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET or MOS) Ideal Structure (NMOS) Symbol (NMOS) G (Gate) SiO (Silicon dioxide) 2 D (Drain) (Source) S G n+ n+ D D BG Si (Silicon) p S S Substrate tied to source B (Body or Substrate) Connected to source or most negative supply Actual Structure (p-substrate, n-well process) G (n-substrate, p-well process) G S D B S D n+ n+ p+ n+ n+ p-well n-substrate p-substrate B Basic Operation of MOSFET S (1) When VB = VS = VG = VD = 0, the S/B and D/B p-n junctions are OFF. The structure has two back-to-back diodes in series. G D n+ n+ p B S D Even VD > VS, no current flows in the structure ⇒ MOS is in cutoff region. VG1 > Vt S Last updated: 2-Oct-03 D ID n+ (2) Now if the gate voltage VG increases to a certain values, Vt = threshold voltage, a channel is formed connecting the source and drain. G n n+ p B 1 ELEC202 – Electronic Circuits II MOS ID If VD is slightly greater than VS , a small current will flow through the channel. MOS is now turn-on and the current is proportional to VGS. VG1 > Vt i.e. IDS ∝ VGS VDS 0 If further increase the VG, a wider channel is formed and more current will flow through the channel. i.e. ID increases with VG. The MOS is now operating in linear region (triode region). S VG2 > VG1 VD1 G VG3 > VG2 ID n n+ ID VG2 > VG1 n+ VG1 > Vt p VDS 0 B Note that IG = 0 as the current cannot flow through the insulator (oxide) layer. (3) If we keep VG constant and further increase VD, the channel resistance increases as the shape of the channel is distorted as shown in the figure. As the channel becomes narrower at the drain side, the channel resistance increases. ⇒ slope decreases ∴ The ID-VDS curve will be bended downward. ID VG VD2 > VD1 n n+ Curve bends as channel resistance increased Almost straight line n+ p B VDS 0 (4) If we further increase the VD until VGD ≦ Vt, the channel is pinched-off and the drain current ID will not be affected by the drain voltage VD. VG n+ ID triode Pinched off VD3 > VD2 saturation linear n n+ Pinched off VDS(sat) ∝ VGS p B 0 Triode region: VGD > Vt, VGS − VDS > Vt Saturation region: VGD < Vt, VGS − VDS < Vt Last updated: 2-Oct-03 VDS(sat) = VGS − Vt is not a constant VDS ∝ ID ⇒ VDS < VGS − Vt ⇒ VDS > VGS − Vt 2 ELEC202 – Electronic Circuits II MOS Modes of Operation VGD Triode region (Linear region) Saturation region (Pinch-off region) Vt 0 Cutoff Vt VGS Saturation region (Pinch-off region) G Equations 1. Cutoff region: ID = 0 2. Linear region: I D = µ n C OX ( ′ = kn ( where D S W 1 2 )[(VGS − Vt )VDS − VDS ] L 2 n+ n+ 1 W 2 )[(VGS − Vt )VDS − VDS 2 L L p µn = mobility of electron Cox = oxide capacitance per unit area W, L = channel width & length of the MOS 3. Pinch-off region: I D = W 1 W µ nCOX ( )(VGS − Vt ) 2 2 L PMOS Transistor Ideal Structure G D Symbol G p+ p+ S S S n B D Substrate tied to source G D B Actual Structure (CMOS process) G G S D B D S n+ n+ n+ p+ p+ n-well p NMOS Last updated: 2-Oct-03 B Operation of PMOS is the same as NMOS except Vt is negative PMOS 3 ELEC202 – Electronic Circuits II MOS Enhancement versus Depletion MOSFET S Enhancement NMOS G ID D S n+ n+ Depletion NMOS G D n n+ p ID n+ p B 0 D D G G S Vt Vt > 0 VGS VGS D B D G G B S S S Non-ideal Characteristic of MOSFET 1. Finite Output Resistance - due to channel-length modulation effect - effective channel length Leff decreases as VDS increases. G S D n+ L p ∆L n+ B Modified Equation 1 W µCOX ( )(VGS − Vt ) 2 (1 + λVDS ) 2 L where λ = 1 V A , VA similar to Early voltage in BJT. ID ID = Typical λ = 0.005-0.3 V−1 ⇒ VA = 33-200 V Vt 0 Vt < 0 B − VA = − 0 1 VDS λ Note: Channel-length modulation effect is more severe in short channel devices (L < 1 µm) 2. Body Effect Threshold voltage depends on the body (substrate) voltage. Vt = Vto + γ ( 2φ f + VSB − 2φ f ) where γ= 2qN Aε S COX γ = body parameter, typical value γ = 0.5 V1/2 φf = Fermi level ≈ 0.3 V NA = doping concentration of the substrate εS = permittivity of silicon = 1.04×10−12 F/cm Last updated: 2-Oct-03 4 ELEC202 – Electronic Circuits II MOS 3. Temperature Effect In BJT, VBE decreases with temperature (~−2mV/oC) ⇒ IC increases with temperature and will cause thermal runaway (i.e. temp ↑, IC ↑ and then temperature further ↑, IC further ↑until the transistor burn out). In MOS, Vt decreases with temperature (~−2mV/oC), and µ decreases with temperature (dominant effect). As a result ID decreases with temp. ⇒ Good for power circuits. Large Signal Model (in pinch-off region) IG = 0 D G D + VGS G 1 W µCOX ( )(VGS − Vt ) 2 2 L − S S DC Analysis Example 1: Find VD, VG, VS, ID, IG and IS. Assume µCox = 20 µA/V2, L = 10 µm, W = 400 µm, Vt = 2 V. First assume the MOS operates at pinch-off region. 400 µ W µCOX ( ) = 20 µ ⋅ = 0.8mA / V 2 10 µ L VG = 0V, IG = 0A, ID = IS −VSS + ID RS + VGS = 0 µC OX W − 5 + 5k ( )(VGS − Vt ) 2 + VGS = 0 2 L 0.8m − 5 + 5k (VGS − 2) 2 + VGS = 0 2 2(VGS − 2) 2 + VGS − 5 = 0 VDD = 5V ID VD IS 2 2VGS − 7VGS + 3 = 0 7 ± 7 2 − 4(2)(3) = 3V 2( 2) ∴VS = 0 − 3V = −3V ⇒ VGS = ID = RD = 10 kΩ RS = 5kΩ −VSS = −5V or 0.5V (rejectedQVGS < Vt ) 0 .8 m 0 .8 m (VGS − 2) 2 = (3 − 2) 2 = 0.4mA = I S 2 2 VD = VDD − IDRD = 5 − 0.4(10) = 1V Check: VGD = VG − VD = 0 − 1= −1V < Vt ∴ MOS is in pinch-off Last updated: 2-Oct-03 5 ELEC202 – Electronic Circuits II MOS Example 2: VDD RD Find VD, VG, VS, ID, IG and IS. RG Calculation is the same as in Example 1. Because IG = 0 and RG will not have any effect in this circuit. RS −VSS Example 3: Now if RD = 20kΩ. VD = VDD − IDRD = 5 − 0.4m(20k) = −3V VGD = VG − VD = 0 – (−3) = 3V > Vt ⇒ MOS is in fact operating in triode region ∴ We should use another equation in the calculation. I D = µC OX ( VDD = 5V RD = 20kΩ W 1 2 )[(VGS − Vt )V DS − V DS ]LL (1) L 2 RS = 5kΩ VDS = VD − VS = VDD − IDRD + VGS ……(2) −VSS = −5V −VSS + IDRS + VGS = 0 … …(3) Solve (1), (2) and (3) to find out ID & VGS. Not that easy, need to use simulation. However, if VGS is known, the calculation will be simpler. Now, VGS = 5V Example 4: W 1 2 )[(VGS − Vt )V DS − V DS L 2 1 2 = 0.8m[(5 − 1)V DS − V DS ] 2 VDD = 5V I D = µC OX ( But RD = 10kΩ Vo V − VDS 5 − VDS I D = DD = RD 10k ⇒ 5 − VDS 1 2 = 0.8m[4VDS − VDS ] 10k 2 1 2 5 − VDS = 8(4VDS − VDS ) 2 VDS = ⇒ 2 4VDS − 33VDS + 5 = 0 33 ± 332 − 4(4)(5) = 0.154V 2( 4) or 8.10V (rejected QVDS > VDD ) 1 2 I D = 0.8[4VDS − VDS ] = 0.485mA 2 V 0.154 = 319Ω On-resistance of the MOSFET = DS = ID 0.485m Last updated: 2-Oct-03 6 ELEC202 – Electronic Circuits II MOS Find ID and VGS. R2 50k VDD = ⋅15 = 5V Since IG = 0, VG = R1 + R2 50k + 100k I D R S + VGS = VG Example 5: VDD = 15V R1 = 100kΩ RD = 5kΩ R2 = 50kΩ RS = 3kΩ µC OX W ( )(VGS − Vt ) 2 + VGS = 5 2 L Then solve for VGS similar to Example 1. Transistor As An Amplifier VDD iD RD vD iD + vgs − vGS 0 + VGS − iD = µCOX W ( )(vGS − Vt ) 2 = k n (vGS − Vt ) 2 = k n (VGS − v gs − Vt ) 2 2 L 2 = k n (VGS − Vt ) 2 + 2k n (VGS − Vt )v gs + k n v gs = I D + 2k n (VGS − Vt )v gs + k n v gs 2 ⇒ id = 2k n (VGS − Vt )v gs + k n v gs ≈ 2k n (VGS − Vt )v gs if 2 2 k n v gs << k n (VGS − Vt )v gs v gs << 2(VGS − Vt ) = 2∆VGS ⇒ the value of the small signal depends on the biasing condition. Set id = gmvgs ; gm is transconductance; W g m = 2k n (VGS − Vt ) = µC OX ( )(VGS − Vt ) L ∂i ∂ µCOX W = or define g m = D [ ( )(VGS − Vt ) 2 ] ∂vGS v =V ∂vGS L 2 v GS But I D = GS =VGS GS W 1 µC OX ( )(VGS − Vt ) 2 ⇒ (VGS − Vt ) = L 2 = µCOX ( W )[(VGS − Vt ) L 2I D µC OX ( W ) L W W )(VGS − Vt ) = 2µCOX ( ) I D ∝ I D L L 2I D 2I D ID or gm = (VGS − Vt ) = = 2 (VGS − Vt ) (VGS − Vt ) (VGS − Vt ) 2 I Compare with BJT, g m = C with VT =26mV VT For MOS, in practice, VGS – Vt ≈ 0.1V ⇒ in general gm(MOS) < gm(BJT) with same power consumption. ⇒ g m = µCOX ( Last updated: 2-Oct-03 7 ELEC202 – Electronic Circuits II MOS Gate Current & Input Resistance at the Gate IG = 0 ⇒ Rin |looking into the gate = ∞, i.e. open-circuit. Source current & Input Resistance at the Source IS = ID and iS = id ∂v gs ∂v gs 1 = = ∴Rin |looking into the source = ∂i S ∂i d gm Voltage Gain vD = VDD – iD RD = VDD – ( ID + id )RD = (VDD – ID RD) − iD RD = VD − iD RD ⇒ vd = −iD RD = −gmvgsRD v Voltage gain = d = − g m R D v gs D Small-signal Model G D + vgs gmvgs ro g m = 2 I D µCOX ( W ) L gmvgs = iS 1 rO = λI D G + iS vgs − − S ro 1 gm S Modeling of body Effect Vt = Vto + γ ( 2φ f + VSB − 2φ f ) Consider the substrate as a “second gate” of the MOSFET ∂i g mb = D ∂v BS v =const ,v =const GS DS We can calculate gmb = χ gm , where χ = ∂vt γ . Typical value of χ = 0.1 to 0.3. = ∂v SB 2 2φ f + VSB Include in the small-signal model G + vgs D gmvgs gmbvbs ro − S Note: gmb can be ignored if the substrate is tied to source. Last updated: 2-Oct-03 8 ELEC202 – Electronic Circuits II MOS DC Biasing in MOS - to provide a constant ID which is insensitive to Vt. A. Classical Biasing IDRS +VGS = VGG VDD where VGG = RG 2 ⋅ VD 0 RG1 + RG 2 RG1 RG2 2I D = VGG W µCox L - RS provides a negative feedback to stabilize ID. - Since IG = 0, RG1 and RG2 can be set to very large to minimize the power lost in the biasing circuit. - May use the same Rule of Thumb as in BJT to determine the voltage across RS, RD and between source and drain. RD RS I D RS + Vt + VDD RD B. Two Supplies - Similar to single supply biasing circuit - High RG is used to establish high resistance to a signal source that may be capacitively coupled to the gate. −VSS C. Self-biasing with resistive feedback - VG=VD ⇒ always operates in pinch-off region. - However, negatives output swing is limited to –Vt. RS RG VDD RG RD RS D. Using Current-Source VDD RD - Commonly used in integrated circuit (IC design) - The most simple and efficient way to bias MOS circuit. RG I −VSS Last updated: 2-Oct-03 9 ELEC202 – Electronic Circuits II MOS Current Mirror W W If = , L 1 L 2 Since IG1 = IG2 = 0, I D = I R ef = W W If ≠ , L 1 L 2 VDD VGS1 = VGS 2 ⇒ I D1 = I D 2 VDD − VGS R VGS 1 = VGS 2 ⇒ IO I R ef 2I D 1 = VDD − Vt − R W µCOX L IRef R M1 IO M2 W I 2 L 2 == I1 W L 1 i.e. The output current ID is related to the reference current Iref by a ratio of the aspect ratio of M2 to M1. E.g. Iref IO1 = Iref W L 1 IO2 = 3Iref W W = L 2 L 1 W W = 3 L 1 L 3 Effect of VO on IO • • In order to operate the current mirror as expected, both transistors should operate in pinch-off region (saturation region). If VO goes below certain value, M2 will go into linear (triode) region and to output current will drop below Iref. IO Iref M1 IO1 Iref 1 rO due to channelmodulation effect Slope = + M2 VO − 0 VO VO(min) VGS VO|Q2 in linear region = VO(min) = VGS − Vt = ∆VGS. Output resistance of the current mirror = RO = Last updated: 2-Oct-03 ∆VO 1 1 = = rO 2 = ∆I O slope λI O 10 ELEC202 – Electronic Circuits II MOS Biasing in Integrated Circuit - use current source (current mirror) (1) Simple Mirror BJT: Iref = (β+2)i IO = βi IO = β β +2 I ref = 1 1+ 2 I ref = β 1 1+ 2 ⋅ VCC − VBE ( on ) R β VDD IRef β = 100 ⇒ 2% error RO = ro 2 R 2i βi VO (min) = VCE ( sat ) IO M2 βi M1 ii E.g. V A = 100V , I O = 1mA ⇒ RO = 100kΩ Including Early Effect ν I C = I S exp BE V T VCE ⋅ 1 + VA I ⇒O I C1 VCE 2 1 + VA = VCE1 1 + VA E.g. V A = 100V , VCE1 = VBE ( on ) = 0.7V If VCE = 10V ⇒ 10 1 + 100 ≈ 1.09 = 0.7 1 + 100 IO I C1 ( 9% error ) In general, I O ≈ nI ref ⇒ I O = 1+ VDD n I n + 1 ref IRef β E.g. β = 100, n = 10 ⇒ ~11% error MOS Since IG = 0, IO = n Iref W L n where n = W L 1 RO = ro2 VO(min) = ∆VGS = VGS − Vt Last updated: 2-Oct-03 IO R ×1 ×n VDD IRef R W M1 L 1 IO M2 W L 2 11 ELEC202 – Electronic Circuits II MOS (2) Simple with Current Gain IO = β i I ref 2 = (β + )i β +1 IO = I ref β 1 ⇒ IO = I ref 2 2 1+ β+ β +1 β ( β + 1) If β = 100 ⇒ 0.02% error RO = ro2 VO(min) = VCE(sat) VCC − 2V BE ( on ) Note: I ref = R (3) Current Source with Emitter Degeneration Assume β is large, IC2R2 + VBE2 = IC1R1 + VBE1 IC2R2 = IC1R1 + VBE1 − VBE2 I I = I C1 R1 + VT ln C1 ⋅ S 2 I S1 I C 2 IO = 1 R2 2 IRef I ref I S 2 ⋅ I ref R1 + VT ln I O I S1 less sensitive to β R β +1 i IO 2i βi βi ii IO IRef M1 not easy to solve, use iteration method M2 R1 R2 Particular case: IS2 = IS1, R2 = R1, ⇒ IO = Iref 1 IS2 = n IS1, R2 = R1, ⇒ IO = n Iref n Note: For small R1, R2 (i.e. small RE, RB) RE, RB « rπ RO ≈ (1 + gm2 R2) rO IR higher output ≈ 1 + O 2 rO VT resistance β RB rπ RE RO = 1 + g m ro rπ + RE + RB RE 26mV = 2.6kΩ gm 1mA If IOR2 = voltage across R2 = 260mV (R2 = 260Ω « rπ) ⇒ RO ≈ 10ro However, VO(min) = VCE(sat) + IOR2 E.g. IC = 1mA, rπ = = 100 ⋅ Advantage compares with simple mirror - Matching of IO & Iref is improved by emitter resistors - RO boost up by (1 + gm2R2) times Last updated: 2-Oct-03 12 ELEC202 – Electronic Circuits II MOS (4) Widlar Current Source IRef I ref I S 2 1 VT ln ⋅ R2 I O I S1 - Not linear equation, must be solved by iteration - Useful for generating very small/large current RO = (1 + gm2R2)rO , R2 « rπ VO(min) = VCE(sat) + IOR2 IO = IO « Iref Q1 Q2 R2 IRef E.g. IS1 = IS2, Iref = 1mA & IO = 10µA 1 1m 10 µ = (26m) ln ⇒ R 2 = 12kΩ R2 10µ (5) Cascode Current Source To increase the output resistance RO = [1 + gm(ro//rπ)]ro ≈ β ro Use small-signal model to calculate the exact value, β RO = IO » Iref Q1 Q2 R1 β IRef β + 1 i β +2 i β +1 Q3 rO 2 VO(min) = VBE(on) + VCE(sat) Q4 (β +2)i Note: Q3 acts as a level shifter (diode) to keep Q2 in active region and enforce VCE1 = VCE2 β2 i β +1 + 2i βi VO Q2 Q1 ii − Disadvantage: β2 i β +1 β ( β + 2) β + 2 β = i+ i+ i β +1 β +1 β +1 IO = I ref IO β2 1 =2 = I ref ( β + 2β ) + ( β + 2) + β 1 + 4 + 2 2 β β worse than the simple current mirror ! (6) Wilson Current Source I ref β ( β + 2)i β +1 β +2 = βi + i β +1 IO = IRef VC1 IO β ( β + 2) β + 2β =2 =2 I ref β + β + β + 2 β + 2 β + 2 2 1 = 1+ Last updated: 2-Oct-03 2 2 β + 2β IO β +2 i β +1 + Q3 βi better than cascode current source (β+2)i Q1 VO Q2 ii − 13 ELEC202 – Electronic Circuits II Because of feedback, RO = MOS β 2 rO (solve using small-signal model) IRef VO(min) = VBE(on) + VCE(sat) ⇒ High output resistance and low sensitively to β. Best in BJT current mirror! Note: IO Q4 Q3 Q1 Q2 Wilson source uses feedback to enforce IO ≈ Iref IO↑ , VBE3 ↑, VC1↑, IC1↑, Ib3↓, IO ↓ Improved Wilson Mirror Q4 enforce VCE1=VCE2 to give a better match of IO to Iref. MOS Current Source (1) Simple - Discussed Before (2) With Current Gain - Not needed in MOS as IG = 0 (3) With Source Degeneration - Similar to the one in BJT IrefR1+VGS1= IOR2+VGS2 2 I ref 2I O I ref R1 + Vt + = I O R2 + Vt + W W µC OX µC OX L 1 L 2 Iref M1 2 I ref 2I O 1 I ref R1 + R1 − ⇒ IO = W W R2 µC OX µC OX L 1 L 2 VO(min) = IO R2 + ∆VGS & RO = (1 + gm2 R2)ro2 M2 R1 M3 (5) Cascode Source - Good in MOS as IG=0, i.e. no matching problem IO = Iref RO=ro4 [1 + (gm4 + gmb4)ro2] + ro2 VO(min) = Vt + 2∆VGS Iref 2(Vt+∆VGS) M1 IO + M4 VO M2 VGS = Vt+∆VGS IO M3 + VO M1 R2 Iref (4) Widlar Source - Similar to the one in BJT - For very large or very small current (6) Wilson Source - Also Good in MOS IO = Iref RO ≈ (gm1 ro1) ro3 VO(min) = Vt + 2∆VGS IO M2 Iref − IO Modified Wilson − Vt+∆VGS Last updated: 2-Oct-03 14 ...
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