ch2_MOS_15-21 - ELEC202 – Electronic Circuits II MOS...

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Unformatted text preview: ELEC202 – Electronic Circuits II MOS Single-Transistor Amplifiers Common-Source Configuration DC Transfer Characteristic (a) Cutoff region VI < Vt & ID = 0 VDD RD VO VI VO = VDD − IORD = VDD (b) Pinch-off region (saturation) (a) VO VI >Vt & VDS >VGS −Vt (b) Slope ∝ Square function VDD 1 W µC OX ( )(VGS − Vt ) 2 2 L 1 W VO = V DD − R D µC OX ( )(VGS − Vt ) 2 2 L ID = VDS(sat) (c) (c) Triode region (linear) VI > Vt & VDS < VGS − Vt 0 Vt W 1 2 )[(VGS − Vt )V DS − V DS ] L 2 W 1 2 − R D µC OX ( )[(VGS − Vt )V DS − V DS ] L 2 VI VGS(sat) I D = µC OX ( VO = V DD Note: (i) In general AV(MOS) (square function) < AV(BJT)(exponential function) (ii) VGS(sat) = VDS(sat) + Vt or VGD(sat) = Vt Small-signal Characteristic Since both source and substrate are grounded (Vbs = 0), gmb is ignored. ii Rin= ∞ Ro = RD//ro v Av = o = − g m ( RD // ro ) vi io + vi − gmvi ro + RD vo − For RD << ro, Av = −gmRD For RD << ro, Av = Av(max) = −gmro = − g m But g m = 2 I D µCOX ( Note: W ) ∝ ID L ∴ Av (max) ∝ 1 ID In BJT AV(max) is independent to IC. Also, for fixed ID, AV (max) ∝ Last updated: 16-Oct-03 VA 1 = −g m ID λI D W i.e. size of the MOSFT L 15 ELEC202 – Electronic Circuits II MOS Common-Gate Configuration VDD vo + vgs RD vo ro − gmvgs vi RD gmbvbs vi Case (i) Substrate tied to source, vbs=0 1 Rin = Ro = RD//ro gm AV = g m ( RD // ro ) Case (ii) Substrate tied to ground, vbs = vgs 1 Rin = Ro = RD//ro g m + g mb AV = ( g m + g mb )( RD // ro ) Common-Drain Configuration (Source Follower) vi VDD + vgs − vi gmvgs Ro′ vo RS ro gmbvbs io′ vo RS Case (i) Substrate tied to source, vbs = 0 Rin = ∞ Ro = RS // 1 gm Av = RS RS + 1 gm = g m RS 1 + g m RS Case (ii) Substrate tied to ground, vbs = −vs = −vo Rin = ∞ v iO ' = − g m v gs − g mb vbs + o = g m vo + g mb vo ro Ro ' = vo 1 1 = ⇒ Ro = RS // io ' g m + g mb g m + g mb vo = RS ( g m v gs + g mb vbs + − vo ) ro = RS [ g m (vi − vo ) − g mb vo ] Last updated: 16-Oct-03 16 ELEC202 – Electronic Circuits II vo ( MOS 1 + g m + g mb ) = g m vi RS AV = For large RS, AV = vo gm RS = = 1 vi g + g + 1 RS + [1 + g mb RS ] m mb RS gm gm 1 = g m + g mb 1 + χ Since typical value of χ = 0.1 to 0.3 ⇒ AV = 0.909 to 0.769 for large RS. Therefore, common-drain configuration is not a perfect source follower if the substrate is not tied to source. Common Source with source degeneration Not commonly used because: 1. Beneficial effect of increasing Rin is irrelevant in MOS. 2. Transconductance of MOS is much lower than BJT. gR will be very small. ⇒ the gain AV = − m o 1 + g m RS VDD RD vo vi RS Active load Common-Emitter Configuration with Resistive load Graphical Representation Load-line Method: V − VCE1 VCC − VO I C1 = CC = RC RC IC1 Load line VCC RC vi IC1 vo VBE4 = Vin4 > Vin3 VBE3 = Vin3 > Vin2 VBE2 = Vin2 > Vin1 VBE1 = Vin1 > VBE(on) 0 Last updated: 16-Oct-03 Load line for large R2 V − VO I C1 = CC RC 2 VCC VCE1 = VO 17 ELEC202 – Electronic Circuits II MOS VCC Common-Emitter with Active load Load-line Method Q3 V V IC2 = F2(VCE2, VBE2) = I S 2 [exp BE 2 ] ⋅ (1 + CE 2 ) V VA2 T Q2 IC2 vo IC1 vi IC1 = F1(VCE1, VBE1) = F1(VCE1, Vin) Q1 R Want to find IC2 as a function of VO = VCE1 Note: IC1 = −IC2 & VCC = VEC2 + VCE1 OR VCE2 = VCE1 − VCC Therefore, IC1 = −IC2 = − F2(VCE1 − VCC, VBE2) where VBE2 is fixed by the mirror and R. Superimpose the IV characteristic curve of Q1. IC2 −F2(VCE2) −IC2 −IC2 −F2(VCE1−VCC) F2(VCE2) VCE VCE2 VCC VCE1 Superimpose the IV characteristic curve of Q1. IC1 = −IC2 VCE1 Load line Vin4 Vin3 VCC VCC − VCE(sat) Vin2 active load Vin1 0 VCC resistive load VCE(sat) 0 VCC VCE1 = VO Small-signal analysis V V // V AP V Ro = ro1//ro2 = AN // AP = AN I C1 I C 2 I C1 I (V // V AP ) 1 (V AN // V AP ) = − AN Av = −gm1Ro = − C1 ⋅ ← independent of IC and gm!!! VT I C1 VT − 50 ≈ −2000 V/V E.g. VAN = VAP = 100 V, AV = VCC 25m IC RC VT If Av = −200V/V & IC = 1 mA, ⇒ RC = 50 kΩ (50V across RC!) V |Av(max)| < CC if VCC = 10 V, |AV(max)| < 400 V/V. VT RC Compare in resistive load, AV = − g m RC = − Last updated: 16-Oct-03 vi IC1 vo 18 ELEC202 – Electronic Circuits II MOS Active Load in MOS Av = −gm (ro1//ro2) V V W = − 2µCOX ( ) I D1 ( AN // AP ) L I D1 I D 2 =− µCOX W 2I D ( L Q3 Q2 vo )V A All NMOS Amplifier Passive load (Resistive load) vi Q1 NMOS load Enhancement load Depletion load PMOS load vo vi VDD vo vi vo vo vi vi Diode-connected enhancement load VGD = 0 ⇒ either in cutoff or pinch-off region. ID = 1 W µCOX ( )(VGS − Vt ) 2 2 L 1 W i = µCOX ( )(v − Vt ) 2 ⇒ square function 2 L 1 Incremental resistance = gm i i + v − v 0 Vt Diode-connected depletion load VGS = 0 ⇒ always on, either in linear or pinch-off. i For v > −VtD, MOS operates in pinch-off region. Note: −VtD is a –ve value. + v DS W 1 v ) I D = µC OX ( )(VGS − VtD ) 2 (1 + − L VA 2 W v 1 2 i = µC OX ( )VtD (1 + ) ⇒ linear function L VA 2 v = I DSS (1 + ) where IDSS = drain-to-source saturation current VA Incremental resistance = ro for v > −VtD. Last updated: 16-Oct-03 i IDSS 0 −VtD v 19 ELEC202 – Electronic Circuits II MOS NMOS Amplifier with Enhancement Load iD1 Load VO VDD − Vt2 Q2 iD2 = iD1 vi Q1 cutoff Q2 pinch-off I II B vo Q1 0 Q1 in pinch-off Q2 in pinch-off vDS1 VDD − Vt2 VDD Q1 in triode Q2 in pinch-off III 0 Vt1 VI VI > VO + Vt1 Biasing point Assume Vt1 = Vt2 = Vt, λ = 0, gmb neglected. For both Q1 & Q2 in pinch-off. 1 W 1 W iD2 = iD1⇒ µCOX ( ) 2 (v − Vt ) 2 = µCOX ( )1 (vi − Vt ) 2 2 L 2 L W L 1 v − Vt = ± (vi − Vt ) W L 2 Since vo = VDD – v, W L 1 vo = VDD − Vt ± (vi − Vt ) W L 2 W V − V + L 1 V − = DD t t W L 2 ← take the –ve one as the gain is –ve W L 1 ⋅ vi W L 2 W L 1 Av = − W L 2 For high gain, Q1 is short & wide and Q2 is long & narrow, typical value |Av| < 10. Last updated: 16-Oct-03 20 ELEC202 – Electronic Circuits II MOS NMOS Amplifier with Depletion load vO iD I VDD IV III Q1 cutoff Q2 triode VDD−|Vt2| Q2 Q1 pinch-off Q2 pinch-off III Q1 triode Q2 pinch-off IV Ro′ vo vi II Q1 0 Av = − gm2vgs2 Vt1 gm1vgs1 − gmb2vbs2 ro2 vo + vgs1 ro1 vgs = 0 vbs2 = −vs2 = −vo vo vi + vi − Av = vI vI > vo + Vt1 vo = − g m1[ro1 // Ro ' ] (Region III only) vi + vgs2 vi −Vt1 0 I VDD Q1 pinch -off Q2 triode II vo g g 1 1 = − g m1 (ro1 // ro 2 // ) ≈ − m1 = − m1 = − χ g m2 χ vi g mb 2 g mb 2 gm1vi ro1 ro2 gmb2vo W L 1 W L 2 Since χ = 0.1 to 0.3 ⇒ 3 to 10 times improvement over enhancement load. Last updated: 16-Oct-03 21 ...
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This note was uploaded on 01/05/2010 for the course EENG 202 taught by Professor P.mok during the Spring '03 term at University of Arizona- Tucson.

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