{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

ch3_digital_01-08

ch3_digital_01-08 - ELEC202 Electronic Circuits II Digital...

Info icon This preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
ELEC202 – Electronic Circuits II Digital Last updated: 28-Oct-03 1 CMOS Digital Circuits Inverter Characteristic Ideal Voltage Transfer Characteristic Typical Voltage Transfer Characteristic V M (voltage midpoint) – input voltage at which the inverter yields an output voltage equal to the input voltage V th (inverter threshold voltage) Noise Margin A B Input A Output B 0 1 1 0 Noise V IH1 V IL1 V OH1 V OL1 V IH2 V IL2 V OH2 V OL2 NM NM Logic 1 Transition region Logic 0 Conditions: V OH > V IH & V OL < V IL NM H = V OH V IH NM L = V IL V OL V IN V OUT 0 V out = V in V M V + V + V M = (V + /2) = V th V OUT 0 V IL High gain region Slope = 1 V OH V M V Omax V OL V Omin V M V IH V + V IN
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
ELEC202 – Electronic Circuits II Digital Last updated: 28-Oct-03 2 Transient Characteristic t PHL = propagation delay from high-to-low t PLH = propagation delay from low-to-high t P = 2 1 (t PHL + t PLH ) t F = fall time t r = rise time Idealized condition: V OH = V DD & V OL = 0 Power Dissipation When there is a switching, the capacitor C will charge up to V + or discharge to 0V. Energy stored in C = 2 2 1 + CV Energy dissipation in each switching = CV 2 + Dynamic Power dissipation P D = f CV 2 + Note: Static Power dissipation P S = V + I Delay-Power Product (DP) - a figure of merit to measure the quality of a particular circuit topology DP = P D t P MOS Inverter Circuit NMOS: Resistor Pull-Up t V OUT 0 t V IN 0 t PHL t PLH t r t F V OL V OL V OH V OH 50% 50% 90% 10% 50% 90% 10% 2 1 (V OL + V OH ) C C V + I V + R V DD V OUT C L V IN V OUT 0 V IL Pinch-off cutoff V OH V M V Omax V DD = V + V OL V Omin V M V IH V + V IN V t linear
Image of page 2
ELEC202 – Electronic Circuits II Digital Last updated: 28-Oct-03 3 Note C L is the loading capacitor, which is simulating the input capacitance to other invertors connected to the output and any parasite capacitance. ) )( ( 1 1 min t DD OX DS D DS DD DS DS O V V L W C V i R where V R R R V = = + = µ - Want V omin close to 0 large MOS device and large R - Increase the NM increase V IL and decrease V IH inverter has high gain increase g m or R because R g r R g V V m O m in out = ) // ( case (i) Increase g m by increase the (W/L) ratio.
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}