ch3_digital_01-08 - ELEC202 – Electronic Circuits II...

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Unformatted text preview: ELEC202 – Electronic Circuits II Digital CMOS Digital Circuits Inverter Characteristic Input A 0 1 1 A Output B 0 B Typical Voltage Transfer Characteristic VOUT Ideal Voltage Transfer Characteristic VOmax VOH VOUT V+ Slope = −1 Vout = Vin High gain region VM VM + VM = (V+/2) V = Vth 0 VIN VOL VOmin 0 + VIN VIL VM VIH V VM (voltage midpoint) – input voltage at which the inverter yields an output voltage equal to the input voltage Vth (inverter threshold voltage) Noise Margin Conditions: VOH > VIH & VOL < VIL Noise VOH1 VIH1 NM VIL1 Last updated: 28-Oct-03 VOH2 VIH2 Logic 1 Transition region VIL2 VOL1 NM NMH = VOH − VIH NML = VIL − VOL VOL2 Logic 0 1 ELEC202 – Electronic Circuits II Digital VIN Transient Characteristic tPHL = propagation delay from high-to-low tPLH = propagation delay from low-to-high 1 1 (VOL+ VOH) tP = (tPHL+ tPLH) 2 2 tF = fall time tr = rise time Idealized condition: ⇒ VOH 50% VOL t 0 VOUT tPHL VOH = VDD & VOL = 0 tPLH 90% 90% 50% 10% 0 VOL tr tF Power Dissipation When there is a switching, the capacitor C will charge V+ up to V+ or discharge to 0V. Energy stored in C = 50% 10% VOH t V+ I 2 1 CV + 2 ⇒ Energy dissipation in each switching = CV + 2 Dynamic Power dissipation PD = f CV + Note: Static Power dissipation PS = V+ I 2 C C Delay-Power Product (DP) - a figure of merit to measure the quality of a particular circuit topology DP = PDtP VOUT MOS Inverter Circuit NMOS: Resistor Pull-Up VOmax VDD = V+ VOH VDD R VOUT VIN cutoff Pinch-off VM CL linear VOL VOmin 0 Last updated: 28-Oct-03 Vt VIL VM VIH + VIN V 2 ELEC202 – Electronic Circuits II Digital Note CL is the loading capacitor, which is simulating the input capacitance to other invertors connected to the output and any parasite capacitance. VO min = - RDS ⋅VDD RDS + R where RDS = 1 1 = ∂iD ∂VDS µC (W )(V − V ) OX DD t L Want Vomin close to 0 ⇒ large MOS device and large R Increase the NM ⇒ increase VIL and decrease VIH ⇒ inverter has high gain V ⇒ increase gm or R because out = − g m ( R // rO ) ≈ − g m R Vin case (i) Increase gm by increase the (W/L) ratio. Problem: increase the parasitic capacitance and slow down the transient response case (ii) Increase R Problem: increase the RC time constant to charge up CL and slow down the tPLH Therefore, in order to increase the voltage gain (or increase the noise margin) without degrading the transient response, we need a constant current with high resistance pull-up circuit (i.e. current source). NMOS: Active Pull-Up With NMOS Enhancement Load ID Q2 ID VIN VO Q1 VO VDD−Vt2 VDD Problem: (1) charging current is not constant. In fact, it decreases as VO increases. 0 (2) Vomax = VDD−Vt2 ⇒ VOH < VDD−Vt2 (3) Large static power dissipation when VIN = VIH (W / L)1 to get high gain (4) Need large (W / L) 2 With NMOS Depletion Load ID Q2 VOUT VIN Q1 0 Last updated: 28-Oct-03 VDD VO 3 ELEC202 – Electronic Circuits II Digital constant current charging until VO > VDD−|VtD| large static power dissipation when VIN = VIH (W / L)1 ratio to ensure a high gain inverter and In both cases, we need to have a large (W / L) 2 Advantage: Problem: Note: to ensure to have a low VO when VIN = VDD. CMOS Inverter For vI = high = VOH iD VDD vi vO iD ≈ 0 vO ≈ 0 rDSN with VGSN = VDD = VOH NMOS VSGP = 0 PMOS vO 0 OR For vI = low = VOL iD VDD with VSGP = VDD PMOS rDSP iD ≈ 0 vO ≈ VDD VGSN = 0 = VOL NMOS vO 0 rDSN = dV DS = dI D 1 µ n C OX ( W ) n (V DD − Vtn ) L rDSP = dVDS 1 = W dI D µ p COX ( ) p (VDD − | Vtp |) L Almost an ideal inverter: 1. VOmin = 0, VOmax = VDD ⇒ large signal swing 2. Static power = 0 in both stages 3. Low resistance path between output terminal and ground / VDD ⇒ less sensitive to noise & other disturbances 4. Active pull-up & pull-down devices ⇒ fast devices 5. High input resistance ⇒ can drive large number of similar inverters with no loss in signal level Last updated: 28-Oct-03 4 ELEC202 – Electronic Circuits II Digital Voltage Transfer Characteristic QN off QP triode QN pinch-off QP triode II VO I In order to have a symmetric transfer characteristics, V DD VOH NMOS is exactly matched with PMOS V DD + | Vtp | W W ⇒ µ n C OX ( ) n = µ p C OX ( ) p & Vth = |Vtp| 2 L L since µn is 2 to 3 times of µp ⇒( III VM W W ) p is 2 to 3 times of ( ) n L L V DD − Vtn 2 µ For same channel length, set =n Wn µ p Wp QN pinch-off QP pinch-off QN triode QP pinch-off IV V VOL 0 VIH V Vth = DD 2 Vt VIL Assume ron & rop is infinite ⇒ a straight vertical line in region III V Vth = DD ⇒ 2 VDD VI QN triode QP off If PMOS and NMOS are not matched. iDN = iDP = 1 µ n COX (W / L) n (VGSn − Vtn )2 = k n (VGSn − Vtn )2 2 ( ) = k (V − V ) = k (V − V − V ) ) = ±(V − V − V ) 1 µ p COX (W / L) p VGSp − Vtp 2 iDN = iDP ⇒ k n (Vth − Vtn ) 2 k n k p (Vth − Vtn ( ) 2 2 p GSp 2 p DD th tp DD th tp Vth 1 + k n k p = VDD − Vtp − k n k p Vtn V th= VDD − Vtp + Vth = 1+ iDP tp vin vO iDN VDD − Vtp + k n k p Vtn 1 + kn k p µ n (W / L) n V µ p (W / L) p tn µ n (W / L) n µ p (W / L) p µ (W / L) n n − 1Vtn VDD + µ p (W / L) p = µ n (W / L) n 1+ µ p (W / L) p 1 V DD . 2 1 For Vth = | Vtp |, kn > kp, Vth < V DD 2 For kn = kp, Vtn < | Vtp |, Vth < Last updated: 28-Oct-03 5 ELEC202 – Electronic Circuits II Digital Input and Output Levels for Matched PMOS & NMOS At VIH, Slope = dVo = −1 dVin 1 2 iDN = µ n COX (W / L) n (v I − Vtn )vo − vo 2 In region IV, ( iDP = µ p COX (W / L) p VDD − v I − Vtp ) 2 For matched PMOS & NMOS, kn = kp & Vtn = |Vtp| 121 2 iDN = iDP ⇒ (v I − Vt )vo − vo = (VDD − v I − Vt ) KKKK(1) 2 2 d (v I − Vt ) dvo + vo − vo dvo = −(VDD − vI − Vt ) dVI dv I dv I At vI = VIH, dVo = −1 ⇒ − (VIH − Vt ) + vo − vo (− 1) = −(VDD − VIH − Vt ) dVI 2vo = 2VIH−VDD 1 vo = VIH − VDD KKKK(2 ) 2 (V IH sub(2)in(1) V1 V 1 2 − Vt )V IH − DD − (V IH − DD ) 2 = (V DD − V IH − Vt ) 2 2 2 2 2 V 2 2 2V IH − 2Vt V IH − V DDV IH + Vt V DD − V IH + V IH V DD − DD = (V DD − Vt ) − 2V IH (V DD − Vt ) + V IH 4 2 V DD 2 2 V IH (−2Vt + 2V DD − 2Vt ) = V DD − 2V DDVt + Vt − V DDVt + 4 2 VIH Last updated: 28-Oct-03 ( ) 1 2 2 5VDD − 12VDDVt + 4Vt 4 1 (VDD − 2Vt )(5VDD − 2Vt ) 1 = = (5VDD − 2Vt ) 8 VDD − 2Vt 8 VIH 2(VDD − 2Vt ) = 6 ELEC202 – Electronic Circuits II Digital Similarly, in region II. 1 W µ n COX (v I − Vtn )2 2 L n 1 1 W 2 = µ p COX VDD − v I − Vtp (VDD − vo ) − (VDD − vo ) 2 2 L p iDN = iDP ( ) 1 (vI − Vt )2 = (VDD − vI − Vt )(VDD − vo ) − 1 (VDD − vo )2 KKKK(1) 2 2 (vI − Vt ) = −(VDD − v I − Vt ) dvo − (VDD − vo ) + (VDD − vo ) dvo dv I dv I iDN = iDP ⇒ d : dv I At VI = VIL, dVo = −1 ⇒ (VIL − Vt ) = VDD − VIL − Vt − VDD + vo − VDD + vo dVI 2VIL = 2vO − VDD vo = VDD + VIL LLLL(2 ) 2 V V 1 1 2 Sub (2) in (1), (V IL − Vt ) = (V DD − V IL − Vt )V DD − DD − V IL − V DD − DD − V IL 2 2 2 2 (V IL − Vt )2 = 2(V DD − V IL − Vt ) V DD V − V IL − DD − V IL 2 2 2 2 2 2 2 2 V IL − 2V ILVt + Vt = V DD − V ILV DD − Vt V DD − 2V ILV DD + 2V IL 3 2 2 V IL (2V DD − 4Vt ) = V DD − V DDVt − Vt 4 1 2 2 V IL (V DD − 2Vt ) = 3V DD − 4V DDVt − 4Vt 8 ( V IL = 1 (V DD − 2Vt )(3V DD + 2Vt ) 8 V DD − 2Vt vo = VIH − In region IV: = 2 V 2 + 2V ILVt − DD + V DDV IL − V IL 4 ) 1 (3VDD + 2Vt ) 8 VDD 2 1 V V 1 5 1 ⇒ VOL = V DD − Vt − DD = DD − Vt = (V DD − 2V t ) 8 8 4 8 4 2 Last updated: 28-Oct-03 7 ELEC202 – Electronic Circuits II In region II: vo = Digital VDD + VIL 2 V DD 3 1 1 7 1 + V DD + Vt = V DD + Vt = (7V DD + 2Vt ) 8 2 8 4 8 4 NM L = V IL − VOL ⇒ VOH = V V 1 3 1 1 1 = V DD + Vt − DD + Vt = DD + Vt = (V DD + 2Vt ) 4 8 4 8 4 4 2 NM H = VOH − V IH SAME 1 7 1 5 1 1 1 = V DD + Vt − V DD + Vt = V DD + Vt = (V DD + 2Vt ) 4 8 4 8 4 4 2 For idealized definition, VOH = VDD , VOL = 0 NM L = V IL − VOL = 1 (3VDD + 2Vt ) 8 NM H = VOH − V IH = V DD − SAME 1 (5V DD − 2Vt ) = 1 (3V DD + 2Vt ) 8 8 Eg. VDD = 5V , Vt = 1V 1 Vth = VDD = 2.5V 2 1 VIH = (5VDD − 2Vt ) = 2.875V 8 1 VIL = (3VDD + 2Vt ) = 2.125V 8 1 VOH = (7VDD + 2Vt ) = 4.625V 8 1 VOL = (VDD − 2Vt ) = 0.375V 8 NM L = NM H = idealized NM L = NM H = 1 (V DD + 2Vt ) = 1.75V 4 1 (3V DD + 2Vt ) = 2.125V 8 Note: For large Noise Margin, use large VDD or OS with large Vt. Last updated: 28-Oct-03 8 ...
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This note was uploaded on 01/05/2010 for the course EENG 202 taught by Professor P.mok during the Spring '03 term at University of Arizona- Tucson.

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