ch3_digital_09-18

ch3_digital_09-18 - ELEC202 – Electronic Circuits II...

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Unformatted text preview: ELEC202 – Electronic Circuits II Digital TRANSIENT RESPONSE Consider the turn-on process iDN linear M F pinch-off E at t = 0+ VDD iON vO QN C at t = 0− 0 Between E&F Since i = −C vO VDD/2 VDD After switching is completed dV dt or (∆t )i = −C∆V ∆V i ∆t = −C t PHL1 = C [V DD − (V DD − Vt )] CVt = 1 1 W W µ n C OX (V DD − Vt )2 µ n C OX (V DD − Vt )2 2 2 L n L n Between F & M, 1 2 1 2 W i DN = µ n C OX (V DD − Vtn )vo − vo = k n ' (VDD − Vt )Vo − vo 2 2 L n i DN dt = −Cdv o 1 2 ⇒ k n ' (VDD − Vt )vo − vo dt = −Cdv o 2 kn ' − dv o 1 dt = = 2 2C 2(V DD − Vt ) 2(V DD − Vt )v o − v o V DD kn ' 1 2 t PHL 2 = ∫VDD −Vt 2C 2(VDD − Vt ) dv o 2(V DD − Vt ) 1 vo − vo 2 2(VDD − Vt ) 1 dvo vo − vo 2 Note ∫ ax dx 1 = ln1 − 2 −x ax Last updated: 3-Nov-03 9 ELEC202 – Electronic Circuits II Digital ⇒ kn ' t PHL 2 2C 2(V DD − Vt ) 1 − V 1 DD 2 = ln 2(V DD − Vt ) 2(V DD − Vt ) 1 − V − V DD t = = 1 2(V DD 4(V − Vt ) − 1 ln DD − Vt ) V DD 1 2(V DD 3V − 4Vt ln DD − Vt ) V DD 1 1 1 − = ln 1 2(V DD − Vt ) 2(V − V ) Vo DD t VDD −Vt V DD / 2 t PHL 2 = 3V − 4V t C ln DD V DD W µ n C OX (V DD − V t ) L n Vt 2C 1 3V − 4V t + ln DD V − Vt 2 V DD W µ n C OX (V DD − V t ) DD L n ∴ t PHL = t PHL1 + t PHL 2 = For usual case, Vt ≅ 0.2V DD t PHL = 1.6C W µ n C OX V DD L n ( E.g. Vt = 1V, VDD = 5V ) (1) To minimize propagation delay: 1. use small loading capacitor W 2. use large ratio L 3. use large VDD 4. use smaller Vt Last updated: 3-Nov-03 10 ELEC202 – Electronic Circuits II Digital Approximation: Assume discharge through a constant current. V C VDD − DD 2 = W 1 µ n COX (VDD − Vt )2 2 L n ∴ t PHL very close to (1) For Vt ≅ 0.2V DD , t PHL 1 C V DD 1.56C 2 = = 1 W W µ n C OX (0.8V DD )2 µ n C OX V DD 2 L n L n Fall time tf ≅ 1.6CV DD C [0.9V DD − 0.1V DD ] = 1 W W µ n C OX (V DD − Vt )2 µ n C OX (V DD − Vt )2 2 L n L n tf ≅ 2.5C W µ n C OX V DD L n For Vt ≅ 0.2V DD , Note: For matched CMOS inverter, t PHL = t PLH & t f = t r CMOS Logic Gates Basic Structure VDD A B C ⇒ Pull up network: make vY = VDD (PMOS devices) Y A B C PUN PDN ⇒ Pull down network: make vY = 0 (NMOS devices) Last updated: 3-Nov-03 11 ELEC202 – Electronic Circuits II Digital Implement logic function OR – transistor in parallel AND – transistor in series PDN (function of A, B, C, ……) PUN (function of A, B, C K ) Y Y = A+B A B Y Y = A+ B A B Y A A Y = AB Y = AB B B Y B Y = A + BC Y = A+BC Y B A A C C Y 2-input NOR Gate Y = A + B = AB PDN ⇒ Y = A + B PUN ⇒ Y = A B 2-input NAND Gate Y = AB = A + B PDN ⇒ Y = AB PUN ⇒ Y = A + B A A Y B Y B Last updated: 3-Nov-03 12 ELEC202 – Electronic Circuits II Digital Complex Gate Y = A( B + CD) C B D A Y = A( B + CD ) = A + B + CD = A + B ⋅ CD = A + B(C + D) A C B D Y PDN ⇒ Y = A( B + CD) PUN ⇒ Y = A + B (C + D) Transistor Sizing Since t P ≈ 1.6C 1 ∝ , W W µC OX ( )V DD ( ) L L the propagation delay of a complex gate depends on the equivalent ( W ) ratio. L As, R DS = 1 µC OX ( W )(V DD − Vt ) L ∝ 1 , W () L the calculation of the equivalent ( Transistors in Series Rseries = rDS1+ rDS2 + … W ) ratio can base on the equivalent RDS. L = 1 1 K K + + K = K[ + + K] W W W W ( )1 ( ) 2 ( )1 ( ) 2 L L L L = K W ( )eq L ⇒( W W W )eq = ( )1 //( ) 2 // K L L L Transistors in Parallel Rseries = rDS1// rDS2 // … = 1 1 K K // // K = K [ // // K] W W W W ( )1 ( ) 2 ( )1 ( ) 2 L L L L = K W ( ) eq L ⇒( W W W ) eq = ( ) 1 + ( ) 2 + K L L L Last updated: 3-Nov-03 13 ELEC202 – Electronic Circuits II Digital Consider a 4-input NOR gate VDD A B C 1 (W / L)p 4 A B D C D Y Pull Down: Best case – 4 NMOS’s turn on (W / L)eq = 4(W / L)n Worst case – only 1 NMOS turn on (W / L)eq = (W / L)n Pull Up: Only 1 case – 4 PMOS’s turn on (W / L)eq = To have matched performance comparable with the inverter in worst case operation, ⇒ (W / L)p of each PMOS should be 4 times the (W / L)po of the inverter and (W / L)n of each NMOS should be the same as (W / L)no of the inverter Since µn ≈ 2µp , for matched PMOS & NMOS, (W / L)p ≈ 2(W / L)n Assume (W / L)no = (W / L) and (W / L)po = 2(W / L)no = 2(W / L) Total size of the PMOS + NMOS = 4 × 4 × 2 (W / L) + 4 × 1 × (W / L) = 36 (W / L) no. of transistor size increment for matching match for mobility For 4-input NAND gate Pull Down: A B C D Y A B C D 1 Only 1 case – 4 NMOS’s turn on (W / L)eq = (W / L)n 4 Pull Up: Worst case – only 1 PMOS turn on (W / L)eq = (W / L)p To have matched performance. ⇒ (W / L)p for 4-input NAND should be the same as (W / L)po of the inverter and (W / L)n for 4-input NAND should be 4 times the (W / L)no of the inverter Again assume (W / L)no = (W / L) and (W / L)po = 2(W / L) Total size of the PMOS + NMOS = 4 × 1 × 2 (W / L) + 4 × 4 × (W / L) = 24 (W / L) ⇒ Area of 4-input NAND < 4-input NOR ∴For IC implementation, NAND gates are more favorable than NOR gates. Last updated: 3-Nov-03 14 ELEC202 – Electronic Circuits II Digital More on switching characteristics Use 2-input NAND gate as an inverter Case 1: Both switch VDD A B Y A B A vO B Case 2: Only A switches Case 3: only B switches VDD VDD A vO B B A vO Pull up: tPLH in case 1 is faster (almost double) than in case 2 & 3. Pull down: tPHL – same as before. NAND gate Voltage Transfer Characteristic Recall for inverter Vth = When both A&B switch p-channel in parallel ⇒ n-channel in series ⇒ Weff is doubled ⇒ kpeff is doubled = 2 kp Leff is the same Weff is the same ⇒ kneff is halfed = ½ kn Leff is doubled VO i.e. shifted to the right 0 VDD A Y M2 M1 Only B switches VDD 1 PMOS is always OFF Y M2 B M1 ⇒ kpeff = kP M2 is in triode M1 is in pinch-off Vth = VDS1 + VDS2 1 PMOS is always OFF ⇒ kpeff = kP M2 is in pinch-off M1 is in triode Vth = VDS1 + VDS2 iD VGS1 = VDD Vth VI V DD − Vtp + k n k p Vtn 1 + kn k p = V DD + ( k n k p − 1)Vtn 1 + kn k p for Vtn = |Vtp| ⇒ Vth = VDD + ( 1 4 (kn k p ) − 1)Vt 1 + 1 kn k p 2 Only A switches ID1 = ID2 0 VDS2 VDS1 iD VGS2 = Vth – VDS1 VDS VGS2 = VDD – VDS1 VGS1 = Vth VDS ID1 = ID2 0 VDS2 VDS1 Last updated: 3-Nov-03 15 ELEC202 – Electronic Circuits II Digital Since M1 & M2 operate in different mode with only A switches and only B switches, the VTC in these two cases are different. kn in Case 3 (only B switches) > in Case 2 VO A switches A&B switch B switches 0 VI MOS as a Switch + − NMOS switch On –resistance rDS = dVDS 1 1 = = dI D dI D dVDS µCOX (W / L)(VGS − Vt ) vC To turn on, we need from VDD + Vt to −VDD + Vt Input signal can be from –VDD to VDD vI RL vO CL to ensure the substrate-to- source and substrate-to-drain p-n junction are reverse biased at all time. Connect to –VDD Problem 1: need control voltage > VDD to ensure turn on to all signal between ±VDD 2: the turn-on voltage depends on the input voltage 3: below the turn-on voltage, the switch is barely turn-off 4: on-resistances are different for different vI (for a fixed vC) CMOS Transmission Gate C +VDD to turn-off −VDD to turn-on p-channel Symbol C vI From −VDD to VDD VDD −VDD n-channel C vO RL CL vI C vO +VDD to turn-on −VDD to turn-off At turn-on, C = VDD, NMOS conducts with vI = −VDD to VDD − Vt C = −VDD, PMOS conducts with vI = −VDD + Vt to VDD Last updated: 3-Nov-03 16 ELEC202 – Electronic Circuits II Digital vI = VDD VDD −VDD VDD vI = 0 −VDD VDD −VDD OFF vO ON fully ON VGS = VDD |VGS| = 2VDD vO ON |VGS| = VDD OFF Fully ON vI = −VDD VGS = 2VDD When −VDD < vI < −VDD+Vt only NMOS is ON Note: When VDD−Vt < vI < VDD Only PMOS is ON Latch When −VDD+Vt < vI < VDD-Vt both NMOS & PMOS are ON Positive feedback to force the voltage at each node to either VOL or VOH. vz Consider VOH vx vz VOL 0 stable point stable point unstable point vx SP Flip-flop R Q R 0 0 1 1 S 0 1 0 1 Qn+1 Qn 1 0 Not Used S Q Last updated: 3-Nov-03 17 ELEC202 – Electronic Circuits II Digital Implemented by 2 CMOS NOR Gate Simplified CMOS implementing SR Flip-Flop Q R Q S Q R Q S Clocked SR Flip-Flop A simpler clocked SR Flip-Flop implemented by pass transistor Clock signal φ S S φ Q φ Q R Q φ R Q Last updated: 3-Nov-03 18 ...
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