ch4_amplifier_01-08 - AMPLIFIERS Two-Transistor Amplifier...

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Unformatted text preview: AMPLIFIERS Two-Transistor Amplifier Common-Collector Common-Emitter (CC-CE) Cascade Configuration vi Rin vi vo Q1 R E1 ii v2 io + v1 rπ1 gm1v1 ro1 − vo + v2 Q2 i2 gm2v2 rπ2 ro2 − can be resistor By inspection, Rin = rπ1 +(β1 + 1) RE1 = rπ1 +(β1 + 1) rπ2 Ro = ro2 β 2 ( β1 + 1) i iv r g r ( β + 1) = Gm = o = o ⋅ 2 = g m 2 π 2 = m 2 π 2 1 vi v2 vi rπ 2 + re1 ( β1 + 1)rπ 2 + rπ 1 ( β1 + 1)rπ 2 + rπ 1 AV = io io i2 = ⋅ = β 2 ( β1 + 1) ii i2 ii Note: Rin and Ai are boosted up by β times using cascade combination. Two-port equivalent circuit Rinc = rπ1 + (β1+1) rπ2 Roc = ro2 β 2 ( β 1 + 1) c Gm = ( β 1 + 1)rπ 2 + rπ 1 CC BC EC VCC E.g. RC AV = −Gm Ro = − β 2 ( β1 + 1) ( RC // ro 2 ) ( β1 + 1)rπ 2 + rπ 1 C vi B vo CC EC Same AV = vo vO v2 r = ⋅ = − g m 2 ( RC // ro 2 ) ⋅ π 2 vi v2 vi rπ 2 + re1 =− Last updated: 17-Nov-03 g m 2 rπ 2 ( β1 + 1)( RC // ro 2 ) ( β1 + 1)rπ 2 + rπ 1 RC vo vi v2 1 Darington Configuration General Form CC CC C B Q1 BC Darlington Q2 EC IBias EC As Emitter-Follower (CC-CC cascade) VCC Rin = rπ1 + (β1+1) [rπ2 + (β2+1) RL] 1 1 1 Ro = re2 + [re1] ≈ [rπ2 + ( β 2 + 1) ( β 2 + 1) g m1 AV = Rin vi vO v2 RL r + ( β 2 + 1) RL ⋅= ⋅ π2 v2 vi RL + re 2 rπ 2 + ( β 2 + 1) RL + re1 Q1 v2 ( β 2 + 1) RL ( β1 + 1)[rπ 2 + ( β 2 + 1) RL ] = ⋅ ( β 2 + 1) RL + rπ 2 ( β1 + 1)[rπ 2 + ( β 2 + 1) RL ] + rπ 1 Q2 vo ( β1 + 1)( β 2 + 1) RL = ( β1 + 1)[rπ 2 + ( β 2 + 1) RL ] + rπ 1 Gm = Ro io io vo ( β1 + 1)( β 2 + 1) =⋅= vi vo vi ( β1 + 1)[rπ 2 + ( β 2 + 1) RL ] + rπ 1 RL io VCC As Common-Emitter io1 Rin = rπ1 + (β1+1)rπ2 β i + β 2ib 2 β1ib1 + β 2 ( β1 + 1)ib 2 i i +i = Gm = o = O1 O 2 = 1 b1 vi vi vi vi = β1 + β 2 ( β1 + 1) Rin = vi io RL vo io2 Q1 β1 + β1β 2 + β 2 rπ 1 + ( β1 + 1)rπ 2 ib2 Q2 Because of the feedback through ro1, Ro cannot be found by inspection At node A, g m1v1 + vo − v2 v2 = ro1 rπ 1 // rπ 2 Since v1 = −v2 , 1 1 vo = v2 ( + g m1 + ) ro1 rπ 1 // rπ 2 ro1 Also, v2 v io = + g m 2v2 + o rπ 1 // rπ 2 ro 2 Last updated: 17-Nov-03 K(1) io + v1 gm1v1 rπ1 vo ro1 − vi = −v2 + v2 A rπ2 gm2v2 ro2 − 2 io = [ 1 + g m 2 (rπ 1 // rπ 2 ) vv2 + o (rπ 1 // rπ 2 ) ro 2 1 1 + g m 2 (rπ 1 // rπ 2 ) 1 1 1 + g m 2 (rπ 1 // rπ 2 ) 1 rπ 1 // rπ 2 io = vo ⋅ + = vo + rπ 1 // rπ 2 ro 2 ro1 1 + g m1 (rπ 1 // rπ 2 ) ro1 1 + g m1 (rπ 1 // rπ 2 ) ro 2 ⇒ v 1 1 + g m 2 (rπ 1 // rπ 2 ) 1 Ro = o = + io ro1 1 + g m1 (rπ 1 // rπ 2 ) ro 2 −1 Special Cases: (i) IBias = IC1 =IC2 ⇒ rπ1 = rπ2, gm1 = gm2, ro1 = ro2 −1 1 1 1 RO = + = ro 2 2 ro1 ro 2 (ii) IBias = 0 ⇒ IC1 = IB2 = rπ = IC2 β2 β1 g m1 ⇒ g m1 = = β1 g m2 g m2 β2 (Q g m = IC ) VT & ro1 = β2ro2 (Q ro = VA ) IC β 2 = β 1 rπ 2 −1 1 1 + g m 2 rπ 2 1 1 1 2+ ≈ = = ro 2 Then, Ro ≈ [ β2 1 1 1 ro 2 3 ro1 1 + g m1rπ 2 + + 2ro1 ro 2 2ro 2 ro 2 As Common-Base – Doesn’t help (in fact, worst than simply CB stage) Summary: Cascade Configuration (i) Rin↑ by β (ii) current gain ↑ by β vo Cascode Configuartion (CE-CB configuration) Rin = rπ1 RO = [1+gm2(rπ2//RE2)]ro2 = (β2+1)ro since RE2 = ro1 » rπ2 & IC1 = IC2 i i G m = o ≅ C1 = g m1 vi vi Summary: Cascode Configuration (i) RO↑ – compare with CE & CB configuration – good for current source – provides high gain (ii) io VBias Q2 RE2 vi Q1 −VEE Better frequency response (shown in Elec 304) Last updated: 17-Nov-03 3 Differential Pairs Emitter-Coupled Pairs DC Characteristic: V BE 1 VT I C1 = I S e VCC RC V and I C 2 = I S e BE 2 VT Since Vid = VBE1 – VBE2 & IC1 + IC2 = αIEE I C1 = α I EE and I C 2 = −Vid VT 1+ e α I EE 1+ e Vid VT v1 + vid − RC − Vod + IC1 IC2 Q1 “E” v2 Q2 IEE, REE Vod = IC1RC – IC2RC = RC (IC1−IC2) = −α IEE RC tanh (−Vid/2VT) Vod αIEERC Small Signal (Using Half-Circuit) (a) Differential-Mode Because of the symmetric circuit, “E” is virtual ground. −αIEERC Input range vid 2 = rπ 1 ii Rid = VCC −v 2 AV 1 = od = − g m1Rod 1 + vid 2 io1 Gm1 = vid 2 Vid 0 2VT −2VT RC v id 2 = g m1 io1 ii − v od 2 Q1 Rod 1 = RC // ro Now Rid = vid v2 = 2 id = 2 Rid 1 = 2rπ 1 ii ii VCC v v2 AVd = od = od = − AV 1 = g m1Rod 1 vid vid 2 Gm d = v od RC 2 io2 Q2 io1 − io 2 1 1 1 = g m1 − (− g m 2 ) = ( g m1 + g m 2 ) = g m vid 2 2 2 Avd = Gmd Rod = g m Rod ⇒ Rod = Rod 1 = RC // rO − v id 2 ??? In fact, when we consider the whole circuit, Gm = 1 gm 2 and Ro = 2(RC//ro) Anyway, the overall gain AV = gm(RC//ro). Note: Ro is the resistance between node A and B. ⇒ RC AB − vod + RC Ro = 2(RC//ro) Last updated: 17-Nov-03 4 (b) Common-Mode Vic increases, IE1&IE2 increase. But for ideal current source, IEE = constant. Since IE1 + IE2 = IEE = constant, voltage at “E” increases and Voc = constant VCC RC IE1 vic ⇒ common-mode transconductance = 0 ⇒ and common-mode gain = 0. In practice, there is no ideal source. Assume the current source has a finite resistance of REE. vic vic IE2 “E” IEE −VEE VCC RC RC Voc VCC RC VOC Q1 Q2 RC vic IEE , REE voc Q1 vic 2REE (1/2)IEE −VEE Ric1 = rπ + (β+1)2REE g m Roc Av1 = − where Roc = RC // ro[1+gm(2REE// rπ)] ≈ RC // (β+1)ro 1 + g m 2 REE Now, vic +vid/2 vic −vid/2 Ric = rπ + (β+1)2REE vic +vid/2 −vid/2 1 Ric = [rπ + (β+1)2REE] 2 ∴Ric depends on how you apply the common voltage source. (c) Common-Mode Rejection Ratio A CMRR = d ≈ 1 + 2 g m REE Acm For good differential pairs, we want: High Ad → large RC ⇒ Active load (otherwise saturated) High CMRR → large REE ⇒ Good current source (use Wilson or Cascode Source) Last updated: 17-Nov-03 5 Signal-Ended Output RC RC RC vO vO −vid/2 +vid/2 −vid/2 +vid/2 [still a symmetric circuit Q same VBE and IC] vo 1 = g m ( RC // ro ) However, not for vid 2 differential output vo 1 = g m ( RC // ro ) vid 2 Active-Load Use active transistor as a load. v Avd = o = g m Ro where Ro = ro2 // ro4 vid Note: If you want to get a –ve gain, you cannot connect the output at the collector of Q1. Why? Avc = 0 (even for non-ideal source). But in practice, Avc ≠ 0 because of the transistors mismatch and finite β & VA values of the BJT. g m vid 2 v1 + vid − Q3 g m vid 2 Q4 g m vid 2 Q1 g v m id vo gmvid Q2 v2 − vod + RD 2 Source-coupled Pairs I D1 = µCOX W ( 2 I D1 RD )(VGS1 − Vt ) 2 = k (VGS 1 − Vt ) 2 L = k (VGS 1 − Vt ) I D 2 = k (VGS 2 − Vt ) ⇒ I D1 − I D 2 = k (VGS 1 − VGS 2 ) = kVid And also ID1 + ID2 = ISS ⇒ Vod = ∆IDRD = ( ID1-ID2)RD = RD µCOX W 2 (1) is linear if vid ≤ ( L 2 I CS 2 − vid µCOX W () L 2 )vid I SS µCOX W 2 ( L 2 equations, 2 unknown K(1) + vid − ISS vod 0 ) for both devices are in pinch-off. vid A few volts (vs 50 mV in BJT) Range depends on ISS & the size of the MOSFET Last updated: 17-Nov-03 6 OUTPUT STAGES - to deliver certain amount of signal power to a load (high current) - large signals, small-signal analysis may not be applicable - minimize output impedance - low signal distortion VCC Class A Output Stage (Emitter Follower output stage) Note: (1) Io is zero when Vo is zero (i.e. IE1 = IQ) vI ⇒ Vi has biasing voltage of VBE1. such that I C1 = I S1e vBE 1 VT Io IR = αI Q IQ Q3 (If vI > VBE1, IC1 > αIQ, IO > 0, VO > 0) (2) IQ » IR with R2 « R1. Q2 R1 Transfer Characteristics vI = VBE1 + vO Q1 R3 vO VO(max) = VCC − VCE1(sat) R2 + RL v O − −VEE Q1 saturated I slope ≈ 1 = VT ln C1 + vO I S1 vI 0 VBE1 VO IQ + RL Q1 cutoff + vO = VT ln RL2 −IQRL2 I S1 RL1 VO(min) = −VCC + VCE2(sat) + IQR2 Q2 saturated ≈ −VCC + VCE2(sat) (1) For large RL = RL1, Io is small and IC1 is relatively constant. ∴VBE1 is relatively constant and slope ≈1. IQ v I ≈ VT ln I + vO ≈ VBE1 + vO S1 v IQ + O RL (2) For small RL=RL2, VT ln I S1 V In this situation, I O = − O = I Q RL dominant and v approaches −∞ as v approaches –I R . I O Q L2 vO and premature clipping occurs. −IQRL2 clipping Last updated: 17-Nov-03 No clipping when VCC − VCE ( sat ) RL2 > IQ 7 Average Output power 1ˆˆ ˆ ˆ Consider sinusoidal signal, PL = VO I O , VO & I O are peak values. 2 Before slipping, PL max 1ˆ ˆ ˆ = VOm I Om where VOm = max load voltage before clipping 2 ˆ I Om = max load current before clipping ˆ (1) For large RL = RL1, VO = VCC − VCE ( sat ) & ˆ V ˆ I Om = Om RL1 2 1 (VCC − VCE ( sat ) ) Output Power, PL = R L1 2 Area (A) Increase RL1, max. output voltage essentially the same & current decreases ⇒ PL decreases. ˆ ˆ (2) For small RC = RL2, I Om = I Q , VOm = I Q RL 2 12 I Q RL 2 Area (B) 2 Decrease RL2, max. output current stays the same & voltage decreases ⇒ PL decreases. Output Power, PL = Graphical Method VO + Vce1 = VCC (IC1−IQ)RL + Vce1 = VCC IC1RL = −Vce1 + VCC + IQRL V 1 IC1 = − Vce1 + ( CC +IQ) RL RL IC1 load line RL = RL2 For maximum output power, PL = Area (C) Q IQ ˆ ˆ ⇒ VOm = VCC – VCE(sat) & I Om = IQ ˆ I Om for (A) 1 1ˆ ˆ PL max = VOm I Om = [VCC − VCE ( sat ) ]I Q RL = RL1 2 2 (C) (B) when RL = RL1 IQ 1 = VCC 0 VCE(sat)1 [2VCC – VCE(sat)2] Vce1 R L 3 VCC − VCE ( sat ) ˆ VCC − VCE ( sat ) VOm for RL = RL2 or R L 3 = IQ Note: It is important to design IQ of the output stage for a particular load. 10 E.g. VCC = 10 V, RL3 = 100 Ω, ⇒ IQ = = 100 mA. 100 Last updated: 17-Nov-03 8 ...
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