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Unformatted text preview: CPSC 121 Lecture 10 January 26, 2009 Menu January 26, 2009 Topics: Multiplexer (MUX) Other Combinational Circuits: — Adders and Decoders Reading: Today: Lab 3 (when available) Next: Epp 2.3, 2.2, 2.4 Reminders: Assignment 1 due Friday, January 30, 17:00 Inclass Quiz 1 Wednesday, February 4 Midterm exam Tuesday, February 24 (evening) READ the WebCT Vista course announcements board Today’s lecture returns to the topic of combinational circuits. We go a little further by introducing circuit elements that are slightly more complex than the logic gates we have seen so far and that serve as building blocks for even more complex circuit elements. First, we look at multiplexers. Multiplexer (MUX) Multiplexer (MUX) Consider the following “black box” circuit specificaton: input a input b input c output y If c is "1" then copy b to y Otherwise, copy a to y Input c plays the role of a control whose value determines whether we select a or b as output Truth Table MUX c b a y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If c is 1, copy b to output y. Otherwise, c is 0 and we copy a to output y Multiplexer (MUX) Here’s one gate symbol used to represent the MUX we have defined: 1 Y A B C Recall: Input C plays the role of a control whose value determines whether we select A or B as output Multiplexer Implementation Task: Determine a circuit that implements a (2 input) MUX Let’s use a Sum–of–Products (SOP) representation 1 Y A B C 2 C B A y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Recall: Input C plays the role of a control whose value determines whether we select A or B as output Multiplexer Implementation (cont’d) The standard SOP representation of our truth table is: Y ≡ C BA + CBA + CB A + CBA For any proposition α , we have the following simplification rule (i.e., logical equivalence): αA + α A ≡ α Thus, we determine Y ≡ C BA + CBA + CB A + CBA ≡ CA + CB A + CBA ≡ CA + CB Multiplexer Implementation (cont’d) Here’s the corresponding circuit Y A C B Multiplexer Implementation (cont’d) Let’s look at timing... Y A C B 3 Y C B A 1 1 1 1 There is a (short) “glitch” (aka “hazard” ) in the output Y NOTE: This glitch is a transient effect. The steady state behaviour of our circuit is fine The “glitch” is related to the (slight) delay caused by the inverter. This changes the timely (slightly) between the two AND gates. Multiplexer Implementation (cont’d) Here’s a safe (aka lenient ) design corresponding to Y ≡ CA + CB + AB Y A C B NOTE: We have added an extra AND gate. It is redundant (with respect to the steady state behaviour) of our MUX. But, it eliminates the “glitch” from our previous implementation One can systematically implement combinational logic using MUX as the only circuit element....
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This note was uploaded on 01/09/2010 for the course CPSC 121 taught by Professor Belleville during the Spring '08 term at The University of British Columbia.
 Spring '08
 BELLEVILLE

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