lecture16

lecture16 - 1 Prof. Aiken CS 143 Lecture 16 1 Register...

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Unformatted text preview: 1 Prof. Aiken CS 143 Lecture 16 1 Register Allocation Lecture 16 Prof. Aiken CS 143 Lecture 16 2 Lecture Outline Memory Hierarchy Management Register Allocation Register interference graph Graph coloring heuristics Spilling Cache Management Prof. Aiken CS 143 Lecture 16 3 The Memory Hierarchy Registers 1 cycle 256-8000 bytes Cache 3 cycles 256k-1M Main memory 20-100 cycles 32M-1G Disk 0.5-5M cycles 4G-1T Prof. Aiken CS 143 Lecture 16 4 Managing the Memory Hierarchy Programs are written as if there are only two kinds of memory: main memory and disk Programmer is responsible for moving data from disk to memory (e.g., file I/O) Hardware is responsible for moving data between memory and caches Compiler is responsible for moving data between memory and registers Prof. Aiken CS 143 Lecture 16 5 Current Trends Power usage limits Size and speed of registers/caches Speed of processors But The cost of a cache miss is very high Typically requires 2 caches to bridge fast processor with large main memory It is very important to: Manage registers properly Manage caches properly Compilers are good at managing registers Prof. Aiken CS 143 Lecture 16 6 The Register Allocation Problem Intermediate code uses unlimited temporaries Simplifies code generation and optimization Complicates final translation to assembly Typical intermediate code uses too many temporaries 2 Prof. Aiken CS 143 Lecture 16 7 The Register Allocation Problem (Cont.) The problem: Rewrite the intermediate code to use no more temporaries than there are machine registers Method: Assign multiple temporaries to each register But without changing the program behavior Prof. Aiken CS 143 Lecture 16 8 History Register allocation is as old as compilers Register allocation was used in the original FORTRAN compiler in the 50s Very crude algorithms A breakthrough came in 1980 Register allocation scheme based on graph coloring Relatively simple, global and works well in practice Prof. Aiken CS 143 Lecture 16 9 An Example Consider the program a := c + d e := a + b f := e - 1 Assume a and e dead after use Temporary a can be reused after e := a + b So can temporary e Can allocate a , e , and f all to one register ( r 1 ): r 1 := r 2 + r 3 r 1 := r 1 + r 4 r 1 := r 1- 1 A dead temporary is not needed A dead temporary can be reused Prof. Aiken CS 143 Lecture 16 10 The Idea Temporaries t 1 and t 2 can share the same register if at any point in the program at most one of t 1 or t 2 is live ....
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This note was uploaded on 01/12/2010 for the course CS 143 at Stanford.

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lecture16 - 1 Prof. Aiken CS 143 Lecture 16 1 Register...

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