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Unformatted text preview: o We’ll use synopsys-A language for describing hardware o Encourages hierarchial design o A simple block a b c (an AND gate) o Each block is a VHDL entity-A VHDL entity should start with these lines Library ieee; Use ieee.std_logic_1146.all; (grab these libraries we need)-Then define the inputs & outputs of the block”: Entity and.gate is port ( a, b : in std.loic; c : out std.logic); end and.gate;-Each statement ends with a “;”-“and gate” is the name of the entity-“port” gives the list of ports-connections to the outside-“a,b” are input ports, “c” is an output-“std.logic” is a signal type that comes with the IEEE library-signals o represents a signal sent along a connection o we’ll use std_logic for most signals o a std)logic signal can have these values & ‘0’ 0—false & ‘1’ 1—true & ‘X’ error | unknown & ‘U’ uninitialised & and 4 others Half adder AND...
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- Spring '97
- CPU cache, Input/output, Memory management unit, VHDL ENTITY, VHSIC hardware Description