{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

soln.sample.quiz2

# soln.sample.quiz2 - (C A.H.Dixon page.2 2 PC clpc(clear PC...

This preview shows pages 1–3. Sign up to view the full content.

CMPT 250 : QUIZ 2 Solutions QUESTION 1: The black-box diagram and characteristic table are: 1 1 0 1 1 1 0 0 Q+ 1 0 1 0 1 0 1 0 C 1 1 0 0 1 1 0 0 S 1 1 1 1 0 0 0 0 Q Q’ Q clk C S QUESTION 2: entity SC-FF is port(S,C,clk: in bit; Q,Qc: out bit); end SC-FF; architecture behav of SC-FF is begin P1: process(clk) is if clk = ’1’ then if S = ’1’ then Q <= 1; QC <= 0; elsif C = ’1’ then Q <= 0; QC <= 1; end if; end if; end process; end behav; (C) A.H.Dixon page. .1

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
QUESTION 3: 1. F3 F2 F1 F0 F F st F3 F2 F1 F0 F<-0 IR<-MDR MDR<-dbus PC<- PC+1 rd,req F <- 1 PC <- 0 st Figure 1: ASM diagram for fetch and state diagram for sequencer It will take 3*25 ns = 75 ns to fetch an instruction.
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: (C) A.H.Dixon page. .2 2. PC: clpc (clear PC) ipc (increment PC) lpc (load PC) (optional) AC: lac (load AC) T1: ac (place AC on bus) IR: lir (load IR) T2: ir (place ir on bus) MDR: lmdr (load MDR) T3: mdr (place MDR on bus) T4: in (place dbus on bus) T5: out (output bus to dbus) F: S (set F to 1) C (clear F to 0) optional: ALU: f0,f1,f2,. . (fn select) 3. st*F0: clpc, S F*F1: r, req F2: lmdr F3: lir, mdr, C (C) A.H.Dixon page. .3...
View Full Document

{[ snackBarMessage ]}

### Page1 / 3

soln.sample.quiz2 - (C A.H.Dixon page.2 2 PC clpc(clear PC...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online