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Unformatted text preview: valid exponent and a significand field of all 0s: 0000 0000 1000 0000 0000 0000 0000 0000 In hex: 0080 0000 3. entity FSM is port(req,err,ack: in bit; z1,z0: out bit); end FSM; architecture behav of FSM is begin proc1: process(req,err,ack) type state is range 1 to 3 variable curr_state: state := 0; begin case curr_state is when 1=> if req=1then curr_state:=2 else curr_state:=1; end if; when 2=> if err=1 then curr-state:=3 else curr_state:=1; end if; (C) A.H.Dixon page. .1 when 3=> if ack=1 then curr_state:=1 else curr_state:=3 end if; end case; case curr_state is when 1=> z1<=0; z0<=1; when 2=> z1<=1; z0<=0; when 3=> z1<=1; z0<=1; end case; end process; end behav; 4. 1 1 A3 A2 A1 A0 R(E)<-S, ack W<-W+1 R<-shr R R(E)>1 S<-A(E) R<-A(W)+B(W) B(E)<-B(E)+1 B(W)<-shr B(W) A(E)<- A(E)+1 A(W)<-shr A(W) = > < A(E):B(E) B<- bus2 A,- bus1 st (C) A.H.Dixon page. .2...
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This note was uploaded on 01/16/2010 for the course CS 251 taught by Professor Various during the Spring '97 term at Simon Fraser.
- Spring '97