Test1.soln

Test1.soln - port(s: in state; st, r0: in bit; rdy, lr,...

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CMPT 250 00-3 : TEST #1 SOLUTIONS Question 1 : r0 n32 Q0 out2 out1 c_in cm up cln clq slq srd ld lr s op2 op1 N>32 R<0 S FA 2 1 N Q CMPL D R 1 0 MUX
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2 Question 2a : n32 n32’ st S3 S2 S1 S0 Question 2b : type state is (S0, S1, S2); entity SEQ is port(st, n32: in bit; s: out state); end SEQ; Architecture behav of SEQ is begin proc: process(clk) variable curr_state: state := S0; begin if clk = ’1’ then case curr_state is when S0 => if st = ’1’ then curr_state := S1; end if; when S1 => curr_state := S2; when S2 => curr_state := S3; when S3 => if n32 = ’1’ then curr_state := S0; else curr_state := S1; end if; end case; s <= curr_state; end if; end process; end behav;
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3 Question 3a S0: rdy S0 * st: lr, cln, ld, clq S1: up, cm, lr, c_in S2 * r0: slq, lr S2 * r0’: slq, Q(0) S3: srd Question 3b : entity CPE is
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Unformatted text preview: port(s: in state; st, r0: in bit; rdy, lr, cln, ld, clq, up, cm, slq, Q0, srd: out bit); end CPE; architecture behav of CPE is begin proc:process(s, st, r0) begin rdy &lt;= 0; lr &lt;= 0; cln &lt;= 0; ld &lt;= 0; clq &lt;= 0; up &lt;= 0; cm &lt;= 0; slq &lt;= 0; Q0 &lt;= 0; srd &lt;= 0; case s is when S0 =&gt; rdy &lt;= 1; if st = 1 then lr &lt;= 1; cln &lt;= 1; ld &lt;= 1; clq &lt;= 1; end if; when S1 =&gt; up &lt;= 1; cm &lt;= 1; lr &lt;= 1; when S2 =&gt; slq &lt;= 1; if r0 = 1 then lr &lt;= 1; else Q0 &lt;= 1; when S3 =&gt; srd &lt;= 1; end case; end process end behav;...
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Test1.soln - port(s: in state; st, r0: in bit; rdy, lr,...

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