This preview shows pages 1–3. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: port(s: in state; st, r0: in bit; rdy, lr, cln, ld, clq, up, cm, slq, Q0, srd: out bit); end CPE; architecture behav of CPE is begin proc:process(s, st, r0) begin rdy <= 0; lr <= 0; cln <= 0; ld <= 0; clq <= 0; up <= 0; cm <= 0; slq <= 0; Q0 <= 0; srd <= 0; case s is when S0 => rdy <= 1; if st = 1 then lr <= 1; cln <= 1; ld <= 1; clq <= 1; end if; when S1 => up <= 1; cm <= 1; lr <= 1; when S2 => slq <= 1; if r0 = 1 then lr <= 1; else Q0 <= 1; when S3 => srd <= 1; end case; end process end behav;...
View Full Document
- Spring '97