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Test2.soln

# Test2.soln - c largest positive number 0 11110 1111111111...

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CMPT 250 00-3 : TEST #2 SOLUTIONS 1. a. load r1, x1 load r2, x0 load r3, y1 load r4, y0 sub r1,r1,r2 sub r3,r3,r4 div r1,r3,r1 store r1, slope b. load r1, x1 sub r1, x0 load r2, y1 sub r2, y0 div r2, r1 store r2, slope c. load x1 sub x0 store temp load y1 sub y0 div temp store slope d. push x0 push x1 sub push y0 push y1 sub div pop slope 2. a. Each register requires 6 bits to be uniquely specified. Three registers require 18 bits in the instruction format. In a 32 bit format, that leaves 14 bits to specify the 14 opcode. Therefore, 2 unique opcodes can be defined. b. 150 instructions requires 8 bits to specify each opcode uniquely. Two registers require 12 bits to be specified. Thus 12 bits remain in the 32 bit word for specifying 12 an address. Therefore there are 2 possible addresses that can be specified.

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2 3. a. The bias for a 5 bit exponent is 15 (01111). 4 b. 22.625 = 10110.101 = 1.0110101 x 2 10 2 The floating point number is 0 10011 0110101000
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Unformatted text preview: c. largest positive number: 0 11110 1111111111 15 = 1.1111111111 x 2 smallest positive number: 0 00001 0000000000-14 = 1.0000000000 x 2 16 d. There are 2 possible binary sequences, but we must exclude sequences of the form 11 x 11111 xxxxxxxxxx. There are 2 such sequences. Except for all 0’2 we must 11 also exclude sequences of the form x 00000 xxxxxxxxxx. There are 2- 1 such 32 11 sequences. Therefore the total number of valid sequences is 2- 2*2 + 1. 4. a. reg field 12 bit offset field 16 bit address field 8 bit value 2 bits mode (6 bits) opcode BYTE 3 BYTE 2 BYTE 1 indexed mode implied mode: direct mode: immediate mode: 3 b. 1 1 1 F3 F2 F1 f <- 0 F <- 0 PC <- PC + 1 IR3 <- M[PC] PC <- PC + 1 IR2 <- M[PC} immed mode implied mode PC <- PC + 1 IR <- M[PC} F...
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