final-02-1-ans - CMPT 250 Final Exam Answers You have 180...

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CMPT 250 Final Exam April 15, 2002 Answers You have 180 minutes to complete this exam. Answer all questions in an answer booklet. Do not hand in your question sheet. There is a total of 75 points on this exam; points for each question are indicated. Read through the entire exam before you begin. There are 12 pages ( not counting this page); make sure you have them all. No books, calculators or any other aids are allowed. Where appropriate, clarity and simplicity of your solutions count, as well as correctness. All “Figures” are at the back of the exam.
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CMPT 250 Final Exam, Apr. 15, 2002 1. [10 points] Suppose we want to create a control circuit to control a garage door opener. The circuit will have the following control inputs. These signals will be 1 when the given condition is true and 0 when it is false: b up : A button has been pushed to raise the door. b down : A button has been pushed to lower the door. sensor : A sensor has detected something under the door—if it’s currently going down, it should go back up. end : The door is all the way up or down—the door should stop. The circuit will have two output signals: motor up : When set, the motor will raise the door. motor down : When set, the motor will lower the door. These signals should never both be set to one; it will burn out the motor. When both are zero, the door will be held in its current position. Draw an ASM diagram that describes this circuit. sensor and motor_down b_down b_up end 0 1 0 0 0 1 1 1 motor_down <- 0 motor_up <- 0 motor_down <- 0 motor_up <- 1 motor_down <- 0 motor_up <- 0 motor_up <- 1 motor_down <- 1 2. [10 points] We want to create a VHDL entity to implement this combinatorial circuit: 1
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CMPT 250 Final Exam, Apr. 15, 2002 Y X A B C Figure 1 contains a VHDL implementation of an AND gate; you can use it for reference. We will start with these lines in our file: library ieee; use ieee.std logic 1164.all; (a) Give an entity declaration for this circuit. (b) Give a behavioural architecture implementation of this entity with T pd of 3 ns for both outputs. library ieee; use ieee.std_logic_1164.all; -- (a) entity circuit1 is port ( A, B, C : in std_logic; X, Y: out std_logic); end circuit1; -- (b) architecture behav of circuit1 is begin X <= (not A) and B and C after 3 ns; Y <= A or (not B) or C after 3 ns; end behav; 2
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CMPT 250 Final Exam, Apr. 15, 2002 3. [10 points] We want to create a VHDL entity containing a JK flip-flop: _ Q Q K clock J The flip-flop should only change its output on the rising-edge of the clock . At each rising edge of the clock, the circuit should examine the J and K inputs and change the output as described here: J K Action Output Assignment 0 0 No Change 0 1 Reset Q 0 , Q 1 1 0 Set Q 1 , Q 0 1 1 Complement Q Q, Q Q We will use the following libraries and entity declaration: library ieee; use ieee.std_logic_1164.all; entity jk is port (
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