Lab 6 - Vin (High) 7.000 V 12V (when current equals zero)....

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ECE 206 Section F10 Experiment 6 Lab Write-up 1) Noise Margin (High) = Vout (High) – Vin (High) Noise Margin (Low) = Vin (Low) – Vout (Low) NAND Vout (High) 10.950 V Vin (Low) 7.250 V Vout (Low) 1.150 V Vin (High) 9.000 V NAND Noise Margin (High) = (10.950-9.000)V = 1.950 V Noise Margin (Low) = (7.250-1.150)V = 6.100 V NOR Noise Margin (High) = (11.812-4.500)V = 7.312 V Noise Margin (Low) = (2.500-1.041)V = 1.459 V CMOS Noise Margin (High) = (10.910-7.000)V = 3.910 V Noise Margin (Low) = (4.750-1.270)V = 3.480 V 2) The power supply for the NAND circuit is 5V and for the CMOS circuit it is 12V. The logic high for the NAND circuit is 5V and the logic high for the CMOS circuit is NOR Vout (High) 11.812 V Vin (Low) 2.500 V Vout (Low) 1.041 V Vin (High) 4.500 V CMOS Vout (High) 10.910 V Vin (Low) 4.750 V Vout (Low) 1.270 V
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Unformatted text preview: Vin (High) 7.000 V 12V (when current equals zero). The logic low for both circuit are 0V (when current is at max for the interval being tested). 3) * 0 = Low , 1 = High The logic function for the complex circuit is: Output = NOT[X*(Y+Z)] . . . or NOT[X and (Y or Z)] I determined this by making the following observations: Row 1 indicates the function includes a NOT. Rows 2-4 indicate that X has an and function with Y and Z. Rows 6-8 indicate that Y and Z have an OR function. 4) See attached 5) See attached 6) By examining the attached graph I determined the transition voltages to be as follows. X Y Z Output 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Circuit Vtr (V) NAND 8 NOR 4.2 CMOS 6.3...
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Lab 6 - Vin (High) 7.000 V 12V (when current equals zero)....

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