DLX instruction set description

Structured Computer Organization (4th Edition)

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Unformatted text preview: 160 4.5 4.4 The 8086 Architecture 8-bit displacement FIGURE 4.1 4 There are four postbyte encodings on the 8086 designated by a 2-H tag. The first three indicate a register—memory instruction, where Mem is the base reg‘siet. _ The iourih form is register—register. The DLX Architecture In many places throughout this book we will have occasion to refer to a computer’s “machine language.” The machine we use is a mythical computer called “MIX.” MIX is very much like nearly every computer in existence, except that is, perhaps, nicer ... MIX is the world 's first polyunsaturated computer. ' Like most machines, it has an identtjying number—the 1009. This number was found by taking 16 actual computers which are very similar to MIX and an which MIX can be easily simulated, then averaging their number with equai weight: [(300 + 050 + 709 + 7070 + U3 + 5530 + 1107 + 1604 + 020 + 3220 + 52000 + 920 + 601 + H800 + PDP-4 + 11 )116] = 1009. The same number may be obtained in a simpler way by taking Roman numerals. _ Donald Knuth, The Art of Computer Programing. Volume 1': Fundamental Algorithm _ Instruction Set Examples and Measurements of Use 161 In this section we will describe a simple loadi’store architecture called DLX (pronounced “Deluxe”). The authors believe DLX to be the world‘s second polyunsaturated computer—the average of a number of recent experimental and commercial machines that are very similar in philosophy to DLX. Like Knuth, we derived the name of our machine from an average expressed in Roman numerals: (AMD 29K, DECstation 3100, HP 850. IBM 801, Intel i860, MIPS MIIZOA, MIPS WIOOO, Motorola 88K, RISC I, SGI 4Di'60. SPARCstation-l, Sun-4H 10, Sun-4,060) I I3 = 560 = DLX. The architecture of DLX was chosen based on observations about the mos: frequently used primitives in programs. More sophisticated (and less performance-critical} functions are implemented in software with multiple instructions. In Section 4.9 we discuss how and why these architectures became popular. Like most recent loadi'store machines, DLX emphasizes - A simple load/store instruction set I Design for pipelining efficiency (discussed in Chapter 6} I An easily decoded instruction set - Efficiency as a compiler target DLX provides a good architectural model for study, not only because of the recent popularity of this type of machine, but also because it is an easy architecture to understand. DLX—Our Generic LoadIStore Architecture In this section, the DLX instruction set is defined. We will use this architecture again in Chapters 5 through 7, and it forms the basis for a number of exercises and programming projects. a The architecture has thirty-two 32-bit general-purpose registers (GPRs); the value of R0 is always 0. Additionally, there are a set of floating-point registers (FPRs), which can be used as 32 single-precision (32-bit) registers, or as even-odd pairs holding double-precision values. Thus, the 64-bit floating-point registers are named F0, F2, F28, F30. Both single- and double-precision operations are provided. There are a set of special registers used for accessing status information. The FP status register is used for both compares and PP exceptions. All movement toffrom the status register is through the GPRs; there is a branch that tests the comparison bit in the FP status register. 162 4.5 The DLX Architecture - Memory is byte addressable in Big Endian mode with a 32-bit address. All memory references are through loads or stores between memory and either the GPRs or the FPRs. Accesses involving the GPRs can be to a byte. to a halfword, or to a word. The FPRs may be loaded and stored with single- .' precision or double-precision words (using a pair of registers for DP). All memory accesses must be aligned. There are also instructions for moving between a FPR and a GPR. I All instructions are 32 bits and must be aligned. - There are also a few special registers that can be transferred to and from the integer registers. An example is the floating-point status register, used to hold information about the results of floating-point operations. Operations There are four classes of instructions: loads and stores, ALU operations, branches and jumps, and floating—point operations. ———_——n_—-—— Example instruction Instruction name Meaning 1W R1,3C(R2] Load word 33.32 3.523;-sz L‘r‘.’ R;,'_OCC(RO) Loadword 3:932 313339;.“ LB 39430“) 1—0wa 33—32 (3:14343333)“ its warez-33: 3.3:: R‘..éG(R3) Loadbyteunsigned 31932 92'? at; 55349333: 1“: 31.431331 Loadhaifword 3;»32 xfiéC+R3}c)'-6 es‘tt-{éC+332%#E:él—REZ _.—.'.: 31:4333) Loadhalfwol'd 33—32 ()36 ##MEéOvRSZé?MEé1+RBE unsigned 3.3 33,5383) Loadfloat F3932 34:53-33: L3 33,5382} Loaddoublc 33%??1h6e 5.559.323 SW 535‘ (Ré) ,R3 Storeword MZECC+34§F32 RB 5? 4'3 (33) , PG Store float ;;:éc.'.‘:3} 932 5-0 SS 4CiR3),FG Storedoublc MEéC+R3:(—32 33; g:44~33:(_32 -._:-_ SI-l 532(32) IrR3 Storehalf A‘E532+R2i“;6 R316. 3- SB 41(33},R2 Storebyte Mi4l+R3E<—e 322$..3: RGURE 4.15 The load and store instructions in DLX. All use a single addressing mode and require that the memory value be aligned. 01 course. both loads and stores are available for all the data types shown. Instruction Set Examples and Measurements of Use 163 ——'-'-————'—--\ . Any of the general-purpose or floating-point registers may be loaded or stored, except that loading R0 has no effect. There is a single addressing mode, base register + 16-bit signed offset. Halfword and byte loads place the loaded Object in the lower portion of the register. The upper portion of the register is filled with either the sign extension of the loaded value or zeros, depending on the opcode. Single-precision floating-point numbers occupy a single floating- point register, while double-precision values occupy a pair. Conversions between single and double precision must be done explicitly. The floating-point format is IEEE 754 (see Appendix A). Figure 4.15 gives an example of the load and store instructions. A complete list of the instructions appears in Figure 4.28 (page 165). All ALU instructions are register—register instructions. The operations include simple arithmetic and logical operations: add, subtract. AND, OR, XOR, and shifts. Immediate forms of all these instructions. with a 16-bitsign-extendec1 immediate, are provided. The operation LHI (load high immediate) loads the top half of a register, while setting the lower half to 0. This allows a full 32-bit constant to be built in two instructions. (We sometimes use the mnemonic LI, standing for Load Immediate, as an abbreviation for an add immediate where one of the source operands is R0; likewise, the mnemonic MOV is sometimes used for an ADD where one of the sources is R0.) There are also compare instructions, which compare two registers (=,¢.<.>,s,2). If the condition is true. these instructions place a 1 in the destination register (to represent true): otherwise they place the value 0. Because these operations “set" a register they are called set—equal, set-not-equal, set-less- than, and so on. There are also immediate forms of these compares. Figure 4.16 gives some examples of the arithmetic/logical instructions. Control is handled through a set of jumps and a set of branches. The four jump instructions are differentiated by the two ways to specify the destination address and by whether or not a link is made. Two jumps use a 26-bit signed offset added to the program counter (of the instruction sequentially following the jump) to determine the destination address: the other two jump instructions specify a register that contains the destination address. There are two flavors of jumps: plain jump. and jump and link (used for procedure calls). The latter places the return address in R31. W Example instruction Instruction name Meaning u——___._—___—____i 3 ADD R1,R2,R3 Add th—R2+R3 ADDI Rl,R2.i-.‘3 Add immediate th—R2+3 J Ll-EI a;.#42 Loadhighimmediate 31<—42##cl5 I SLLI R1,R2,#5 Shift left logical R;<——32<<5 5 ; SLT R1,R2,33 Setlessthan if (R2<R3} th—l i else Rle—O FIGURE 4.16 Examples of arithmeticliogicai instructions on DLX, both with and without immediates. 164 4.5 The DLX Architecture Example instruction Instruction name Meaning ! W i J name Jump PCt—name; ((PC+4)—223) S name < ' : ({Pc+4i+22=) i . - JAL name Jumpandhnk R31(—pC+4; PCt—name; (team—235) 5 name < {(Pc+4)+225; : JALR R2 Jump and link register R3lt—PC1-4; PCt—RZ JR R3 Jump register pc(_R3 _i ; BEQZ R4,name Branchequalzero if [R4==O} PCFname; (J'I (recast—215) 5 name < ((Pc+4)+21 ) i susz R4,name Bmhnoieqmlzem if (“1:01 PC(—name; ”semi—2‘”) s name < ((PC+4)+2-3) FIGURE 4.1? Typical control-flow instructions in DLX. All control instructions. except jumps to an address in a register. are PC-relative. If the register operand is H0, the branch is unconditional, but the compiler will usually prefer to use ajump with a longer ofiset over this “unconditional branch." All branches are conditional. The branch condition is specified by the in- struction, which may test the register source for zero or nonzero; this may be a data value or the result of 3 compare. The branch target address is specified with j a 16-bit signed offset that is added to the program counter. Figure 4.1? gives some typical branch and jump instructions. Floating-point instructions manipulate the floating-point registers and indicate whether the operation to be performed is single or double precision. Single-precision operations can be applied to any of the registers, while double- precision operations apply only to an even-odd pair (e.g.. F4, F5). which is designated by the even register number. Load and store instructions for the floating-point registers move data between the floating-point registers and memory both in single and double precision. The operations MOVF and MOVD copy a single-precision (MOVE) or double-precision (MOVD) floating-point register to another register of the same type. The operations MOVFPZl and MOVIZFP move data between a single floating-point register and an integer register; moving a double—precision value to two integer registers require two instructions. Integer multiply and divide that work on 32-bit floating-point registers are also provided, as are conversions from integer to floating point and vice versa. The floating-point operations are add, subtract, multiply, and divide; a suffix D is used for double precision and a suffix F is used for single precision (e.g., ADDD, ADDF. SUBD, SUBF, MULTD, MULTE', DIVD, DIVE"). Floating-point compares set a bit in the special floating-point status register that can be tested with a pair of branches: BFPT and BFPF, branch floating point true and branch floating point false. Figure 4.18 contains a list of all operations and their meaning. Instruction Set Examples and Measurements of Use 165 —————-—————____—____—__—___ I Instruction type i opcode Instruction meaning ' ——-——————-_—____—__________— Data transfers Move data between registers and memory, or between the integer and F? or special registers; only memory address mode is 16-bit displacement 4- contents of a GPR I LB, LBU , SB Load byte, load byte unsigned. store byte LH, LHU, Si—l Load halfword, load halfword unsigned. store halfword _ I’LW, SW [Dad word. store word (toffi'om integer registers) i LE, LD , SF , SD Load SP float, load DP float, store SP float. store DP float MOVE 2 S , MOVSZ I Move fromIIo GPR tolfrom a special register MOVE , MOVD Copy one floating-point register or a DP pair to another register or pair HOVFPB I , MOVI 2F}? Move 32 bits fromlto FP regiSIers toi‘from integer registers i Arithmetic 1 Logical Operations on integer or logical data in GPRs; signed arithmetics trap on overflow ADD, ADDI , ADDU, ADDUI Add. add immediate (all immediates are 16 bits): signed and unsigned I SUB, SUBI , SUBU, SUBUI Subtract. subtract immediate: signed and unsigned MULT, MULTU , D W , DIVU Multiply and divide, signed and unsigned: operands must be floating-point registers; all operations take and yield 32-bit values AND , AND I And, and immediate 4 0R, ORI , XOR, XORI Or, or immediate. exclusive or, exclusive or immediate LHI Load high immediate—loads upper half of register with immediate I ELL, SRL, SRA, SLLI , SRLI , Shifts: both immediate (s I) and variable form (5 l: shifts are shift left logical, sm right logical, right autumn? _ ’ Set conditional: “_" may be LT, GT, LE, GE, EQ, NE Control Conditional branches and jumps; PC-relative or through register BEQZ , BNEZ Branch GPR equalfnot equal to zero; 16-bit offset from PC+4 I ‘ BFP'I', srpr Test comparison bit in the FP status register and branch: 16-bit offset from PC+4 J, JR Jumps: 26-bit offset from PC (J) or target in register (JR) 1 i—JAL, JALR Jump and link: save PC+4 to R31. target is PC-relative (JAL) or a register (JALR) TRAP Transfer to operating system at a vectored address; see Chapter 5 REE Return to user code from an exception; restore user mode; see Chapter 5 1 floating point Floating-point operations on DP and SP formats Add DP. SP numbers ; ADDD, ADDF % ' SUBD, SUB}? Subtract DP. SP numbers —————_—___H_.—_____—___—___ MULTD , MULTE‘ Multiply DP, SP floating point ———.——__—____—____—______ DIVD, DIVF Divide DP. SP floating point ————_—._._—___—__—____ CVTF2D, CVTF2 I , CVTD2F, Convert instrucrions: CV’l‘ny converts from type 1-: to type y, where x and y are one .- MD2I , CVTIZF, CUTI2D of I (Integer), D (Double precision). or P (Single precision). Both operands are in the FP registers r————4———————————————— ! D, F DP and SP compares: ““__ may be LT, GT, LE, GE, EQ, NE; sets comparison bit in FF status register . _._l FIGURE 4.18 Complete list of the instructions in DLX. The formats of these instructions are shown in Figure 4.19. This list can also be found in the back inside cover. 166 4.5 The DLX Architecture Instruction Format All instructions are 32 bits with a 6-bit primary opcode. Figure 4.19 shows the instruction layout. l - type instruction 6 5 5 16 Ian— Encodes: Leads and stores of bytes. words. half-words All immediates {rd — r31 on immediate} Conditional branch instnmions (rs1 is register. rcl unused: Jump register. Jump and link register (rd = 0. rs = destination. immediate = O) R - type instruction Register—register ALU operations: rd - m1 tune r32 Furction encodes thedata path operation: Add. Sub . . . _ Remote special registers and moves J — type instruction 6 26 Jump and jump and link Trap and RFE FIGURE 4.19 Instruction layout tor out. All instructions are encoded in one of three types. Machines Related to DLX Between 1985 and 1990 many loadi'store machines were announced that are similar to DLX. Figure 4.20 describes the major features of these machines. All have 32-bit instructions and are loadr‘store architectures; the figure lists their differences. These machines are all very similar—if you’re not convinced, try making a table such as this one comparing these machines to the VAX or 8086. DLX bears a close resemblance to all the other loadfstore machines shown in Figure 4.20. (See Appendix E for a detailed description of four loadr‘store machines closely related to DLX.) Thus, the measurements in the next section will be reasonable approximations of the behavior of any of the machines. In fact, some studies suggest that compiler differences are more significant than architectural differences among these machines. ...
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