ilp4 - Exposing More ILP These techniques were originally...

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Exposing More ILP These techniques were originally motivated by VLIW , which needs tons of ILP to work at all – but useful for superscalar/dynamic/speculative processors, as well. oftware Techniques Software Techniques – Software Pipelining – Trace Scheduling Hardware/Software Technique – Predicated execution CSE 240A Dean Tullsen Compiler support for ILP: Software ipelining Pipelining bservation: if iterations from loops are independent then can get Observation: if iterations from loops are independent, then can get ILP by taking instructions from different iterations Software pipelining: reorganizes loops so that each iteration is made from instructions chosen from different iterations of the original loop Iteration 0 Iteration 1 Iteration 2 Iteration 3 Iteration 4 Software- pipelined iteration CSE 240A Dean Tullsen W Pipelining Example SW Pipelining Example Software Pipelined D 0 0(R1) Unrolled 3 times 1 LD F0,0(R1) 2 ADDD F4,F0,F2 D (R1) F4 LD F0,0(R1) ADDD F4,F0,F2 LD F0,-8(R1) 1 LP: SD 0(R1),F4; Stores M[i] 3 SD 0(R1),F4 4 LD F6,-8(R1) 5 ADDD F8,F6,F2 6 SD -8(R1),F8 2 ADDD F4,F0,F2; Adds to M[i-1] 3 LD F0, F0,-16(R1); loads M[i 16(R1); loads M[i-2] 2] 4 SUBI R1,R1,#8 NEZ 1 LP 7 LD F10, F10,-16(R1) 16(R1) 8 ADDD ADDD F12,F10,F2 F12,F10,F2 9 SD -16(R1),F12 16(R1),F12 0 UBI 1,R1,#24 5 BNEZ R1,LP SD 0(R1),F4 ADDD F4,F0,F2 SD -8(R1),F4 10 SUBI R1,R1,#24 11 BNEZ R1,LOOP CSE 240A Dean Tullsen Compiler Support for ILP: race Scheduling Trace Scheduling Creates long basic blocks by finding long paths in the code CSE 240A Dean Tullsen
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Trace Scheduling Parallelism across IF branches vs. LOOP branches Two steps: Trace Selection ± Find likely sequence of basic blocks ( trace ) of (statically predicted) long sequence of straight-line code Trace Compaction ± Squeeze trace into few VLIW instructions ± Need bookkeeping code in case prediction is wrong CSE 240A Dean Tullsen Predication : HW support for More ILP Avoid branch prediction by turning branches into conditionally executed instructions : (aka predicated instructions) dc,a,b(x) => if (x) then a = b + c else NOP add c, a, b (x) if (x) then a b c else NOP – If false, then neither store result nor cause exception – Expanded ISA of Alpha, MIPS, PowerPC, SPARC have
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ilp4 - Exposing More ILP These techniques were originally...

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