ilp3 - HW support for More ILP Hardware Speculative...

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HW support for More ILP peculation allow an instruction to issue that is dependent Speculation : allow an instruction to issue that is dependent on branch, without any consequences (including exceptions) if branch is predicted incorrectly (“HW undo”) Often combined with dynamic scheduling Tomasulo: allow speculative bypassing of results – When instruction no longer speculative, write results ( instruction commit or instruction retire ) – execute out-of-order but commit in order – Requires some kind of intermediate storage CSE 240A Dean Tullsen Hardware Speculative Execution Need HW buffer for results of uncommitted instructions: reorder buffer – Reorder buffer can be operand source nce operand commits result is Once operand commits, result is found in register – 3 fields: instr. type, destination, value – Use reorder buffer number instead of reservation station as “name” of result structions commit in order Instructions commit in order – As a result, its easy to undo speculated instructions on mispredicted branches or on xceptions CSE 240A Dean Tullsen exceptions Four Steps of Speculative omasulo Algorithm Tomasulo Algorithm 1. Issue —get instruction from FP Op Queue If reservation station and reorder buffer slot free, issue instr & send operands & reorder buffer no. for destination. Operands may be read from register file or reorder buffer. t i d( EX ) 2. Execution —operate on operands (EX) When both operands ready then execute; if not ready, watch CDB for result; when both in reservation station, execute i t l t i h ti (WB) 3. Write result —finish execution (WB) Write on Common Data Bus to all waiting FUs & reorder buffer; mark reservation station available. ommit d t i t ith d lt 4. Commit —update register with reorder result When instr. at head of reorder buffer & result present, update register with result (or store to memory) and remove instr from reorder buffer. CSE 240A Dean Tullsen omasulo cle 0 ROB Tomasulo cycle 0 ADDD F4, F2, F0 Instruction Queue Loop: MULD F8, F4, F2 ADDD F6, F8, F6 SUBD F8, F2, F0 UBI ADDD F6, F8, F6 SUBI … SUBD F8, F2, F0 Q F0 F2 0.0 2.0 ADDD F4, F2, F0 SUBI BNEZ …, Loop MULD F8, F4, F2 F4 F6 F8 4.0 6.0 8.0 1 2 1 FP adders FP mult’s 3 2 integer CSE 240A Dean Tullsen
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omasulo cle 1 ADDD F4 - ROB 0 Tomasulo cycle 1 ADDD F4, F2, F0 Instruction Queue 1 2 3 4 Loop: BNEZ MULD F8, F4, F2 ADDD F6, F8, F6 SUBD F8, F2, F0 UBI SUBI SUBD F8, F2, F0 Q F0 F2 0.0 2.0 5 6 SUBI BNEZ ADDD F6, F8, F6 MULD F8, F4, F2 F4 F6 F8 4.0 ROB0 6.0 8.0 ADDD 2.0 0.0 1 2 1 ROB0 FP adders FP mult’s 3 2 integer CSE 240A Dean Tullsen omasulo cle 2 ADDD F4 - ULD 8 ROB 0 Tomasulo cycle 2 ADDD F4, F2, F0 Instruction Queue MULD F8 - 1 2 3 4 Loop: SUBI MULD F8, F4, F2 ADDD F6, F8, F6 SUBD F8, F2, F0 UBI BNEZ ADDD F4, F2, F0 Q F0 F2 0.0 2.0 5 6 SUBI BNEZ ADDD F6, F8, F6 SUBD F8, F2, F0 F4 F6 F8 4.0 ROB0 6.0 8.0 ROB1 ADDD 2.0 0.0 MULD ROB0 2.0 1 2 1 ROB0 ROB1 FP adders FP mult’s 3 2 integer CSE 240A Dean Tullsen omasulo cle 3 ADDD F4 - ULD 8 ROB 0 Tomasulo cycle 3 ADDD F4, F2, F0 Instruction Queue MULD F8 - ADDD F6 - 1 2 3 4 Loop: MULD F8, F4, F2 ADDD
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ilp3 - HW support for More ILP Hardware Speculative...

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