bpredict - Looking for Instruction Level Parallelism...

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ranch Prediction Branch Prediction or sometimes you just have to guess CSE 240A Dean Tullsen Looking for Instruction Level arallelism (ILP) Parallelism (ILP) We want to identify and exploit ILP – instructions that can potentially be executed at the same time. Branches are 15-20% of instructions plications? Implications? ± ± Can only keep the pipeline full if we can consistently keep fetching well past unresolved branches. Can only exploit high levels of parallelism if we consistently have multiple in the processor at ce CSE 240A Dean Tullsen once. Importance of Branch Prediction MIPS R2000 -- branch hazard of 1 cycle, 1 instruction issued per cycle – delayed branch ext generation - cycle hazard, 1- instructions issued next generation 2 3 cycle hazard, 1 2 instructions issued per cycle – cost of branch misprediction goes up Pentium 4 CSE 240A Dean Tullsen Branch Prediction Easiest ( static prediction ) – always not taken, always taken – forward not taken, backward always taken –c ompiler predicted (branch likely, branch not likely) Next easiest ( 1-bit dynamic ) – remember last taken/not taken per branch (1 bit) bh i t d – per branch approximated ± per I cache line ± use part of address – what happens on a loop? for (I=0;I<5;I++) { loop: … CSE 240A Dean Tullsen } bnez r1, loop:
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2-bit branch prediction has 4 states instead of 2, allowing for more information out tendencies about tendencies. Loops? CSE 240A Dean Tullsen Two different 2-bit schemes Strongly Taken 11 Weakly Taken 10 en not taken taken Weakly Not Taken 01 ecrement wh e ement when Strongly Not Taken De Incr CSE 240A Dean Tullsen 00 Branch History Table has limited size 2 bits by N (e.g. 4K) uses _____ bits of branch address to choose entry HT branch address BHT what happens when table too small?
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This note was uploaded on 01/21/2010 for the course CSE240A 662015 taught by Professor Tullsen,deanmichael during the Fall '09 term at UCSD.

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bpredict - Looking for Instruction Level Parallelism...

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