a3 - UCSD CSE240A Fall 2009 Homework 3 Answer Key...

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Unformatted text preview: UCSD CSE240A Fall 2009 Homework 3 Answer Key H&P 2.2 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Cycle | Instruction −−−−−−|−−−−−−−−−−−−−−−−−−−−−− 1 | Loop: LD F2,0(Rx) 2 | <stall> 3 | <stall> 4 | <stall> 5 | I0: MULTD F2,F0,F2 6 | <stall> 7 | <stall> 8 | <stall> 9 | <stall> 10 | I1: DIVD F8,F2,F0 11 | I2: LD F4,0(Ry) 12 | <stall> 13 | <stall> 14 | <stall> 15 | I3: ADDD F4,F0,F4 16 | <stall> 17 | <stall> 18 | <stall> 19 | <stall> 20 | <stall> 21 | I4: ADDD F10,F8,F2 22 | I5: SD F4,0(Ry) 23 | I6: ADDI Rx,Rx,#8 24 | I7: ADDI Ry,Ry,#8 25 | I8: SUB R20,R4,Rx 26 | I9: BNZ R20,Loop The loop body would require 26 cycles to execute. P1. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− The number of entries in the BHT must be between 2^7 and 2^13 (inclusive). P2. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− a. Suppose both branches, A and B, have the following pattern TTTNNN and are interleaved like this: ABAB... b. Suppose one branch, A, is always taken and another, B, is always not taken (patterns TTT... and NNN...) and are interleaved like this: ABAB... c. Note: there are a number of reasonable answers here. What follows is one. Given any two branches, they are not likely to be correlated, given that correlation usually only happens between branches in close proximity. Because most alias branches typically have nothing to do with each other, they branch outcomes of each can be seen as random noise to the other. The predictor works by guessing what a branch will do based on the last few executions, and by introducing noise, it will likely obscure that history. P3. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Begin execution cycle Instruction In−order | Out−of−order −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−|−−−−−−−−−−−−− l.d F2, 1000(r2) 1 |1 add.d F6, F2, F4 3 |3 add.d F10, F6, F8 8 |8 addi r2, r2, #8 add.d F12, F2, F14 lw r3, 2000(r5) beqz r3, loop 9 10 11 13 | | | | 2 4 5 7 The in−order case takes 13 cycles for one loop iteration. The out−of−order case takes 8 cycles for one loop iteration (note: 7 cycles may also be a reasonable answer). The speedup is 13/8 = 1.625. P4. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− a. No. b. Instruction | Issue cycle | Execute cycle | CDB write cycle −−−−−−−−−−−−−−−−−−−−−−|−−−−−−−−−−−−−|−−−−−−−−−−−−−−−|−−−−−−−−−−−−−−−− Loop: LD F2,0(Rx) | 0 |1 |4 I0: MULTD F2,F0,F2 | 5 |6 | 10 I1: DIVD F8,F2,F0 | 6 | 11 | 21 I2: LD F4,0(Ry) | 7 |8 | 11 I3: ADDD F4,F0,F4 | 12 | 13 | 15 I4: ADDD F10,F8,F2 | 13 | 22 | 24 I5: SD F4,0(Ry) | 14 | 16 |− I6: ADDI Rx,Rx,#8 | 15 | 16 | 16 I7: ADDI Ry,Ry,#8 | 16 | 17 | 17 I8: SUB R20,R4,Rx | 17 | 18 | 18 I9: BNZ R20,Loop | 18 | 19 |− c. Instruction | Issue cycle | Execute cycle | CDB write cycle −−−−−−−−−−−−−−−−−−−−−−|−−−−−−−−−−−−−|−−−−−−−−−−−−−−−|−−−−−−−−−−−−−−−− Loop: LD F2,0(Rx) | 0 |1 |4 I0: MULTD F2,F0,F2 | 1 |5 |9 I1: DIVD F8,F2,F0 | 2 | 10 | 20 I2: LD F4,0(Ry) | 3 |4 |7 I3: ADDD F4,F0,F4 | 4 |8 | 10 I4: ADDD F10,F8,F2 | 5 | 21 | 23 I5: SD F4,0(Ry) | 6 | 11 |− I6: ADDI Rx,Rx,#8 | 7 |8 |8 I7: ADDI Ry,Ry,#8 | 8 |9 | 11 I8: SUB R20,R4,Rx | 9 | 10 | 12 I9: BNZ R20,Loop | 10 | 13 |− d. There are a couple of ways to calculate this. Here is one way. Since we are only considering the first iteration of the loop, the performance gain for register renaming is 1 cycle (22 cycles vs. 21 cycles). ...
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