a2 - UCSD CSE240A Fall 2009 Homework 2 Answer Key P1.

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: UCSD CSE240A Fall 2009 Homework 2 Answer Key P1. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 1 2 3 4 5 6 7 8 9 10 11 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 1 lw R3,100(R5) IF ID EX M− WB \| 2 add R6,R3,R2 IF ID () −>EX M WB v 3 sub R9,R3,R8 IF () ID EX− M WB \ 4 lw R1,2000(R9) IF ID >EX M− WB \ 5 add R5,R4,R3 IF ID EX | M WB | 6 addi R7,R1,#8 IF ID −>EX M WB Notes: − () represents a bubble. − There is data forwarding between the Mem stage of instruction 1 and the Execute stage of instruction 2 in cycle 5. − There is forwarding through the register file in cycle 5 between instructions 1 and 3. − There is forwarding between the Execute stage of instruction 3 and the Execute stage of instruction 4 in cycle 7. − There is forwarding between the Mem stage of instruction 4 and the Execute stage of instruction 6 in cycle 9. P2. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− The steady−state CPI is 2.5 cycles per instruction. P3. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− The sw instruction is moved into the delay slot and its displacement is changed from 0 to −4. I will accept some other re−orderings (or no re−ordering), as long as they are reasonable. The steady−state CPI is 8/6 = 1.33 cycles per instruction. P4. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− The CPI is 1.1425 cycles per instruction. P5. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 1 2 3 4 5 6 7 8 9 10 11 12 13 14 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 1 lw R3,100(R5) IF ID EX M1 M2 WB \| 2 add R6,R3,R2 IF ID () () >EX M1 M2 WB v 3 sub R9,R3,R8 IF () () ID EX M1 M2 WB \ 4 lw R1,2000(R9) IF ID >EX M1 M2 WB \ 5 add R5,R4,R3 IF ID EX M1 |M2 WB \ 6 addi R7,R1,#8 IF ID () EX M1 M2 WB Notes: − () represents a bubble. − There is data forwarding between the M2 stage of instruction 1 and the Execute stage of instruction 2 in cycle 6. − There is forwarding through the register file in cycle 6 between instructions 1 and 3. − There is forwarding between the Execute stage of instruction 3 and the Execute stage of instruction 4 in cycle 8. − There is forwarding between the M2 stage of instruction 4 and the Execute stage of instruction 6 in cycle 11. P6. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Move | Num | Instruction −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Y |1 | add R1, R2, R3 |2 | sub R5, R2, R3 |3 | and R7, R5, R2 Y |4 | lw R8, 1000(R5) |5 | beq R7, R15, label: |6 | nop |7 | add R6, R7, R5 |8 | sub R5, R7, R5 Y |9 | lw R9, 2000(R2) | 10 | ... Y | 11 | label: add R9, R7, R5 | 12 | addi R5, R0, #0 W1. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Intel Nehalem Intel Core 2 Duo AMD Opteron AMD Phenom 16 14 12 12 stages stages stages stages * Integer pipeline lengths ...
View Full Document

This note was uploaded on 01/21/2010 for the course CSE240A 662015 taught by Professor Tullsen,deanmichael during the Fall '09 term at UCSD.

Ask a homework question - tutors are online