Cache2 - Improving Cache Performance Average memory-access time = Hit time Miss rate x Miss penalty(ns or clocks Reducing Misses Classifying Misses

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Improving Cache Performance Average memory-access time = Hit time + Miss rate x Miss penalty (ns or clocks) 1. Reduce the miss rate, 2. Reduce the miss penalty, or py , 3. Reduce the time to hit in the cache. CSE 240A Dean Tullsen Reducing Misses Classifying Misses: 3 Cs How To Measure Compulsory —The first access to a block is not in the cache, so the block must be brought into the cache. These are also called cold start misses or first reference misses . Misses in infinite cache l Capacity —If C is the size of the cache (in blocks) and there have been more than C unique cache blocks accessed since this cache was last accessed. Non-compulsory misses in size X fully associative che Conflict —Any miss that is not a compulsory miss or capacity miss must be a byproduct of the cache mapping algorithm. A conflict miss occurs because too many ti e blocks are mapped to the same cache set cache Non-compulsory, non-capacity active blocks are mapped to the same cache set. misses CSE 240A Dean Tullsen 3Cs Absolute Miss Rate CSE 240A Dean Tullsen How To Reduce Misses? Compulsory Misses? Capacity Misses? onflict Misses? Conflict Misses? What can the compiler do? CSE 240A Dean Tullsen
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Reduce Misses via Larger Block Size 16K cache, miss penalty for 16-byte block = 42, 32-byte is 44, 64-byte is 48. Miss rates are 3.94, 2.87, and 2.64%. Which gives best performance (lowest CSE 240A Dean Tullsen ,, g p ( AMAT)? Reduce Misses via Higher Associativity Beware: Execution time is only final measure! – Will Clock Cycle time increase? – Hill [1988] suggested hit time external cache +10%, internal + 2% for 2-way vs. 1-way CSE 240A Dean Tullsen Example: Avg. Memory Access Time Miss Rate vs. Miss Rate Example: assume CT = 1.10 for 2-way, 1.12 for 4-way, 1.14 for ay vs CT direct mapped 8-way vs. CT direct mapped Cache Size Associativity B) AMAT (KB) 1-way 2-way 4-way 8-way 1 7.65 6.60 6.22 5.44 2 5.90 4.90 4.62 4.09 60 95 57 19 4 4.60 3.95 3.57 3.19 8 3.30 3.00 2.87 2.59 16 2.45 2.20 2.12 2.04 32 2.00 1.80 1.77 1.79 64 1.70 1.60 1.57 1.59 128 1.50 1.45 1.42 1.44 CSE 240A Dean Tullsen Reducing Misses by emulating ssociativity Victim Cache associativity: Victim Cache HR of associative + access time of direct mapped? dd b ff t h ld d t Add buffer to hold data recently discarded from cache Jouppi [1990]: 4-entry victim pp [ ] y cache removed 20% to 95% of conflicts for a 4 KB direct apped data cache mapped data cache CSE 240A Dean Tullsen
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Reducing Misses by HW Prefetching of struction & Data Instruction & Data E.g., Instruction Prefetching – Alpha 21064 fetches 2 blocks on a miss – Extra block placed in stream buffer – On miss check stream buffer Works with data blocks too: – Jouppi [1990] 1 data stream buffer got 25% misses from 4KB cache; 4 streams got 43% – Palacharla & Kessler [1994] for scientific programs for 8 streams got 50% to 70% of misses from 2 64KB, 4-way set associative caches f t hi li t b d idth th t b Prefetching relies on extra memory bandwidth that can be used without penalty CSE 240A Dean Tullsen Reducing Misses by W refetching ata SW Prefetching Data Data Prefetch – Load data into register (HP PA-RISC, IA64, Tera)
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This note was uploaded on 01/21/2010 for the course CSE 661930 taught by Professor Freund,yoav during the Fall '09 term at UCSD.

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Cache2 - Improving Cache Performance Average memory-access time = Hit time Miss rate x Miss penalty(ns or clocks Reducing Misses Classifying Misses

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