ch7 - CS 7103 Advanced Operating Systems Louisiana State...

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CS 7103 Advanced Operating Systems Louisiana State University Rajgopal Kannan
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Rajgopal Kannan 1. Uniform Memory Access (UMA) 2. Non-Uniform Memory Access (NUMA) Network MM MM PE PE Network MM PE MM PE Cache Cache Cache Cache
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Rajgopal Kannan Virtual Memory Space MM MM MM MM MM MM Frame Offset Page Table Entry
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Rajgopal Kannan 1. Temporal and Spatial locality of references may be exploited using cache 2. Scalability may be improved by using improved network and/or by using cache. 3. DSM helps the application programmer by providing communication transparency. 4. Programmers are more familiar with shared memory. Further many software are available for single processor and multiprocessor shared memory systems.
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Rajgopal Kannan The performance of a DSM may be improved by 1. Placing a data block in appropriate memory module, 2. By migrating data block to an appropriate memory module and 3. by replicating block. The performance of migration and replication strategies are measured by hit ratio. Block-migration strategies suffer from block-bouncing problem. Both block-migration and block-replication strategies suffer from the problem of false-sharing.
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Rajgopal Kannan In a distributed system, it is not possible to enforce uniprocessor-like coherency for shared data items. 1. There is no global clock. Therefore, it is not possible to determine latest write. 2. There will always be delays (non-deterministic). Hence we use some weaker consistency model for shared data in distributed environment. The programmer is supposed to know what kind of consistency is guaranteed and act accordingly.
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Rajgopal Kannan If the user can not give any synchronization information, then general access consistency models are used. The general access consistency models are 1. Atomic consistency (usual uniprocessor consistency, a read never gets stale data) 2. Sequential consistency 3. Causal consistency 4. Processor consistency 5. Slow memory consistency.
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Rajgopal Kannan The operation of all processors are executed in some sequential order and the operations of each individual processor are executed in the order specified by its program. P1: W(X)1 P2: W(Y)2 P3: R(Y)2 R(X)0 R(X)1
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Rajgopal Kannan Only causally related writes must appear in same order to all processors.
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ch7 - CS 7103 Advanced Operating Systems Louisiana State...

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