CSE120 Simulation Lab 5 - 1.0 Introduction The objective of...

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1.0 Introduction The objective of this lab is to transform the brainless microprocessor that I have already created and allow it to function without any external control besides controlling the clock and reset inputs. Also, it is to enter a program in memory and then have the program execute properly. The expected learning outcomes of this lab are to design a PROM to control the microprocessor, create the instruction set for the PROM, put an instruction set in memory and then execute the instruction set. 2.0 Operation of Complete Microprocessor The complete microprocessor differs in operation from the brainless microprocessor because it runs without having someone control all of its various inputs and outputs. The complete microprocessors add and address generation circuit and a controller to automate much of the manual labor of the brainless microprocessor. The addition of the controller allows for the processor to read instructions from memory and control the various inputs to the various components of the processor. This is done by storing the instructions in the PROM that knows how the change the inputs based up the given opcode read from memory. This processor contains opcodes for Load the ACC with a value, adding a value to the ACC, and stopping the program. The other addition is the address generation circuit. This accesses the next address in memory so that the program in memory can continue to be read and ran. With the first clock pulse, the first memory location is read and the PROM updates the inputs to the various areas of the processor. If the opcode it reads from memory has an operand, the memory location is incremented and that value is either loaded in the ACC or added to the ACC. These commands continue until the value of the memory address contains the opcode to stop. At this time, the next state of the PROM is the same as the current state and the PROM is in an infinite loop and will only reset manually. The next page has a circuit diagram of the complete microprocessor.
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CLR CLK EN Register_ U Accumulator L EN° EN° BUFFER_ ° A ° A ° A ° A ° EN ° EN ° BUFFER_ ° EN ° EN ° BUFFER_ ° A ° A ° A ° A ° A ° A ° A ° A ° A ° A ° A ° A ° A ° A ° A ° A ° X CLR CLK EN Register_ u A ° A ° A ° A ° EN ° EN ° BUFFER_° AD °° AD °° AD °° AD °° CLR CLK EN Register_ u A ° A ° A ° A ° L L L L L L L L L L L A B C D E F L L L L L L L L L L A B C D E F L L L L L L L L L L A B C D E F L L L L L L L L L L A B C D E F L Address Bus X (A) Data Bus L (B) Accumulator X ALU EN° EN° BUFFER_ ° e Output L RAM L Address r L Address r EN° EN°
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