CSE120 Hardware Lab 3

# CSE120 Hardware Lab 3 - Introduction In this lab the...

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R S Q Q' Introduction In this lab, the expected learning objectives were to gain experience in building and using latches, flip-flops, and registers and using these skills to lead into building a 2-bit binary up counter. After the completion of the lab, I will understand the operations of the S-R and D latch, the use of the active-high and active-low latches, using the D and J-K flip-flop for larger circuits, how de-bouncing switches work, and using J-K flip-flops for registers and binary up counters. Experiment Results Task 3-1: Building an Active-High S-R Latch Task 3-1: Task Statement In the task, I was asked to build an S-R latch that was active-high. I was also asked to verify the correctness of my work by testing the circuit. Task 3-1: Work Preformed For this task, I used the diagram given in the lab manual to build the latch. The design consists of two NOR gate that have the output of one being on the inputs of the other. Below is circuit diagram for the latch that I built. Figure - Circuit Diagram of S-R Latch To test the output of the latch, I used the LED lights on the circuit board. Below are the results of these tests. They matched the expected values. S R Q Q’ 0 0 Q Q’ 0 1 0 1 1 0 1 0 1 1 0 0 Table - Truth Table from S-R Latch Tests

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Q Q' D EN that the R and S inputs of the latch are never the same. This latch is called a data latch because it is actually used to store data. Task 3-3: Build a D Latch with Enable

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CSE120 Hardware Lab 3 - Introduction In this lab the...

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