CSE120 Hardware Lab 5

CSE120 Hardware Lab - S3 00 S4 10 1 1 1 1 1 Combinational Logic Combinational Logic Flip-Flop Ar ray I nput Output Clock S1 S3 0/00 1/00 0/00 1/00

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Unformatted text preview: S3 00 S4 10 1 1 1 1 1 Combinational Logic Combinational Logic Flip-Flop Ar ray I nput Output Clock S1 S3 0/00 1/00 0/00 1/00 1/10 0/01 Combinational Logic Combinational Logic Flip-Flop Ar ray I nput Output Clock Flip-Flop Ar ray 1.0 Problem Statement The given task for this project was to develop a synchronous sequential machine to function as a device to keep track of the score for a game of screwball. Screwball was explained as a game where each time the ball was put into play that either Player 1 or Player 2 would score one point. The game would end when one player is ahead by 2 points. Below is a list of the design specifications that were given along with assumptions that were made to complete the design. Design Specifications: → The design will feature a synchronous, sequential machine → Because the design is synchronous, all of flip-flops will run off the same clock The only input for the game is whether Player 1 or Player 2 scored because it is assumed that someone scores each time ball is in play → The design needs a reset control to initialize the machine back to the first state → The output needs to indicate when a player has won and which player won 2.0 First Design: Principles and Description The first design was designed as a Moore machine. The input, Y, was defined as a 0 for Player 1 scoring, and a 1 for Player 2 scoring. The output, Z1 Z0, was defined as 00 for neither player winning the game, 01 for Player 1 being the winner, 10 for Player 2 being the winner, and an output of 11 would not be used. There will be five different states, defined below in a state definition table. State Valu e Meaning S0 000 Reset, even scoring S1 001 P1 ahead by 1 S2 010 P1 ahead by 2 S3 011 P2 ahead by 1 S4 100 P2 ahead by 2 S5 101 Not used S6 110 Not used S7 111 Not used Table - State Definition Table for Moore Design The initial state would represent the beginning of the game, the score being even, or a reset state. States S1 and S2 would represent Player 1 being ahead by 1 and 2 points. States S3 and S4 represent Player 2 being ahead by 1 and 2 points. The remaining states would not be used. Below is a state diagram showing the relationship between each of the states. Figure - State Diagram for Moore Design The state diagram shows how at S0, the next state can either be S1 or S3 depending on whether Player 1 or Player 2 scored. Then you can see that if the same play scores again to will move to state S2 or S4. However, if the other player scores, the score is now even and back at S0. When the state is at S2 or S4, the out indicates which player wins. Then the next score will go back to state S1 or S3, depending on the first score of the next game....
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This note was uploaded on 01/26/2010 for the course CSE 120 taught by Professor Matar during the Spring '08 term at ASU.

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CSE120 Hardware Lab - S3 00 S4 10 1 1 1 1 1 Combinational Logic Combinational Logic Flip-Flop Ar ray I nput Output Clock S1 S3 0/00 1/00 0/00 1/00

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