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Unformatted text preview: Introduction In this lab, the expected learning objective of this lab is to gain experience using LogicWorks to build and debug circuits and subcircuits that perform mathematical operations and route data. After the completion of the lab, I will be able to design, build, test, debug, and embed the following type of circuits: 1 and 4 bit adders, 2to1 multiplexer, a 4bit, 2to1 multiplexer, and a 1to2, 2to4, and 4to16 decoder. Experiment Results Task 21: Design a Full Adder Using AND/OR/NOT Logic Task 21: Task Statement In the task, I was asked to design both the canonical POS and SOP form for both the SUM and Cout functions of a full adder only using AND, OR, and NOT gates. Task 21: Work Preformed For this task, I used the truth table for the full adder given in the lab manual to derive the SUM and Cout functions of the full adder in both the POS and SOP forms. Below in Table 1 is the truth table for the full adder. Ci n A B SUM Cout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table  T ruth Table for Full Adder After examining the truth table, the following Boolean expression were derived. For the POS form, the SUM = (CinAB)(CinA’B’)(CinAB’)(CinA’B) and the Cout = (CinA)(CinB)(AB). For the SOP form, the SUM = Cin’A’B+Cin’AB’+CinA’B’+CinAB, and the Cout = ACin+BCin+AB. In determining which form to use, I don’t think it really matters as both would require the same number of gates. Task 21: What I Learned In this task, I learned how to use a truth table to derive the Boolean expressions necessary to build a full adder. I also was able to learn how to determine whether I should use the POS or SOP form to do so. A B Cin SUM CRY Task 22: Build, Debug, and Test a 1Bit Full Adder Task 22: Task Statement In the task, I was to build a 1bit adder using only AND, OR, and NOT gates using the SOP form for the Cout function and then a 3input XOR gate for the SUM function. Then I was to embed this circuit in a subcircuit and test the circuit for later use. Task 22: Work Preformed For this task, I used the SOP form from Task 1 for the Cout and a 3input XOR gate for the SUM function. I did this using the setup in Figure 1 below. Figure  Circuit Diagram of Full Adder I then tested the outputs of this circuit and produced the following t ruth table found in Table 2. Ci n A B SUM Cout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table  T ruth Table for Full Adder Cin B A CRY SUM FA_1 Finally, I embedded this circuit in a subcircuit for later use. Below in Figure 2 is this subcircuit....
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This note was uploaded on 01/26/2010 for the course CSE 120 taught by Professor Matar during the Spring '08 term at ASU.
 Spring '08
 MATAR

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