CSE120 Simulation Lab 3

CSE120 Simulation Lab 3 - INC A0 A1 A2 A3 CRY Y0 Y1 Y2 Y3...

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Unformatted text preview: INC A0 A1 A2 A3 CRY Y0 Y1 Y2 Y3 INC_4 A3 A2 A1 A0 /~Pass NOT/~NEG Y3 Y2 Y1 Y1 Y0 CRY Introduction In this lab, the expected learning objective of this lab is to gain experience using pre-created circuits from previous labs to create a fully functions arithmetic and logic unit. After completing this lab, I will be able to build, test, debug, and imbed all of the components of an ALU, understand how all the operations work within this unit, know the input values and how they affect the output of the ALU, and understanding how gate delay affects the ALU. Experiment Results Task 2-1: Build the NOT/NEG Circuit Task 2-1: Task Statement In the task, I was asked to build a NOT/NEG circuit for my ALU. I was asked to use the design given in the lab manual, test the circuit, and add embed the circuit in the subcircuit for later use. Task 2-1: Work Preformed For this task, I used the design given to me in the lab manual to build the NOT/NEG circuit. This involved passing all the A inputs values through an XOR gate with the /~Pass input. Then I took the output of that and wired it to the A inputs of the 4-bit incrementor. The increment input was wired from the result of a AND gate with the inputs of /~Pass and the complement of NOT/~NEG. Below is the circuit diagram from this work. Figure - Circuit Diagram of NOT/NEG After building the circuit, I embedded the circuit in a subcircuit and proceeded to test the outputs. For the tests, I decided to used the same A input with all 4 combinations of the /~Pass and NOT/~NEG inputs. I also NOT/~NEG /~Pass A0 A1 A2 A3 CRY Y0 Y1 Y2 Y3 NOT/NEG 1 1 1 0 1 2 3 4 5 6 7 8 9 A B C D E F decided to used a different A input that would required the CRY value to output 1 to ensure that this would function properly. Below is the imbedded circuit and the test cases and values. Figure - Imbedded NOT/NEG Subcircuit A / ~Pas s NOT/~N EG Y CR Y Functionality Pass-Through 1 Pass-Through 1 1 Two’s Complement 1 1 F One’s Complement F F Pass-Through F 1 F Pass-Through F 1 1 Two’s Complement F 1 1 One’s Complement Table - Tests for NOT/NEG Circuit Task 2-1: What I Learned A/~B B0 B1 B2 B3 A0 A1 A2 A3 Y0 Y1 Y2 Y3 MUX_4 A/~B B0 B1 B2 B3 A0 A1 A2 A3 Y0 Y1 Y2 Y3 MUX_4 Cin B0 B1 B2 B3 A0 A1 A2 A3 Cout Y0 Y1 Y2 Y3 FA_4 Cin OR/~ADD...
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This note was uploaded on 01/26/2010 for the course CSE 120 taught by Professor Matar during the Spring '08 term at ASU.

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CSE120 Simulation Lab 3 - INC A0 A1 A2 A3 CRY Y0 Y1 Y2 Y3...

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