CSE120 Simulation Lab 4

CSE120 Simulation Lab 4 - 1.0 Introduction In this lab I...

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1.0 Introduction In this lab, I constructed a brainless microprocessor in LogicWorks. I completed the design with three different types of memory and various communications busses. A human could carry out simple operations by controlling the processor. After the completion of this lab, I was able to build and understand a 4-bit register and buffer. I was also able to build and test a simulated central procession unit, ROM, RAM, and an output port. I also learned how to build and test a address decoding circuit. Overall, I was able to control the microprocessor by myself to carry out all of its simple operations. 2.0 Brainless Microprocessor The brainless microprocessor built in this lab was a simple processor that needed a human to operate all of its inputs. In total, there are 14 different inputs to the microprocessor. 4 belong to the various memory cells M0, M1, M2, and M3. One is the Address Bus which controls which of the memory cells is being used at a given time. Two are the Read and Write input that govern whether the processor is in a read or a write mode. One is the clock that is used for all of the registers. One is the reset that can reset all of the buffers. Three, Logic/~Arith, /~Invert, /~A_Only, control the ALU. Load ACC enables the accumulator in the CPU and ACC to Data Bus enables the buffer in the CPU to change the value of A on the DB data bus. The flow of the microprocessor is once the user has changed which location in ROM is going to be accessed, that buffer outputs its value to the DB data bus and then is it the A input of the ALU of the CPU. Then the operations will occur in the ALU and be passed to the accumulator. The accumulator passes its value to the buffer if the ACC to Data Bus is high and the new value is on the data bus. For writing to the OP display, the Write must be high and then the value of A on the data bus will be outputted to the screen. As there are many different inputs, many test had to be done to ensure that the processor works as specified. On the next page, a full diagram of the processor is given and on the following page are the tests done on the processor.
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CLR CLK EN A0 A1 A2 A3 Y0 Y1 Y2 Y3 Register_4 Accumulator B0 B1 B2 B3 5 EN2 EN1 BUFFER_4 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 DECODER_16 0123 4567 89AB CDEF +5V 1 AD00 AD01 AD02 AD03 X Address Bus (A) Data Bus (B) Accumulator ALU A0 A1 A2 A3 B0 B1 B2 B3 Output 0 RAM 3 Address 0 Address 2 Address 1 Address 3 /~A_Only /~Invert Logic/~Arith Cin Cout AB0 RM0 M30 M20 M10 M00 OP0 AB1 RM1 M31 M21 M11 M01 OP1 AB2 RM2 M32 M22 M12 M02 OP2 AB3 RM3 M33 M23 M13 M03 OP3 AL0 AL1 AL2 AL3 Reset Clock ACC to Data Bus Load ACC Read Write /~Inv ert DB FP
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Figure - Diagram of Complete Brainless Microprocessor Because there are so many inputs, it is assumed that M0 is set to 3 and M1 is set to 5. The other memory cells are left to 0.
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CSE120 Simulation Lab 4 - 1.0 Introduction In this lab I...

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