lec4 - Lecture 4 Yield Analysis and Product Quality s s s s...

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Copyright 2001, Agrawa VLSI Test: Lecture 4 1 Lecture 4 Yield Analysis and Product Quality Yield and manufacturing cost Clustered defect yield formula Defect level Test data analysis Example: SEMATECH chip Summary
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Copyright 2001, Agrawa VLSI Test: Lecture 4 2 VLSI Chip Yield A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield . Yield is denoted by symbol Y . Cost of a chip: Cost of fabricating and testing a wafer ────────────────────────── Yield × Number of chip sites on the wafer
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Copyright 2001, Agrawa VLSI Test: Lecture 4 3 Clustered VLSI Defects Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77
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Copyright 2001, Agrawa VLSI Test: Lecture 4 4 Yield Parameters Defect density ( d ) = Average number of defects per unit of chip area Chip area ( A ) Clustering parameter (
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This note was uploaded on 01/26/2010 for the course ECE 682 taught by Professor Tom during the Spring '10 term at University of South Dakota.

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lec4 - Lecture 4 Yield Analysis and Product Quality s s s s...

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