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# lec7 - Lecture 7 Fault Simulation s s s s Problem and...

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Copyright 2001, Agrawa VLSI Test: Lecture 7 1 Lecture 7 Fault Simulation Problem and motivation Fault simulation algorithms Serial Parallel Deductive Concurrent Random Fault Sampling Summary

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Copyright 2001, Agrawa VLSI Test: Lecture 7 2 Problem and Motivation Fault simulation Problem: Given A circuit A sequence of test vectors A fault model Determine Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Motivation Determine test quality and in turn product quality Find undetected fault targets to improve tests
Copyright 2001, Agrawa VLSI Test: Lecture 7 3 Fault simulator in a VLSI Design Process Verified design netlist Verification input stimuli Fault simulator Test vectors Modeled fault list Test generator Test compactor Fault coverage ? Remove tested faults Delete vectors Add vectors Low Adequate Stop

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Copyright 2001, Agrawa VLSI Test: Lecture 7 4 Fault Simulation Scenario Circuit model: mixed-level Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults Signal states: logic Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits Timing: Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback
Copyright 2001, Agrawa VLSI Test: Lecture 7 5 Fault Simulation Scenario (Continued) Faults: Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault- dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large

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lec7 - Lecture 7 Fault Simulation s s s s Problem and...

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