Architectural approach for reducing power

Architectural approach for reducing power - An...

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Unformatted text preview: An Architectural Approach for Reducing Power and Increasing Security of RFID Tags Shenchih Tung, Advisor: Alex K. Jones Email: shtst8@pitt.edu, akjones@ece.pitt.edu Department of Electrical and Computer Engineering, University of Pittsburgh Estimated Graduation Date: Fall 2007 I. INTRODUCTION Radio Frequency Identification (RFID) technology is cur- rently employed for a variety of applications such as RFID- based wireless payment, healthcare, homeland security, asset management, etc. Due to newer privacy requirements and increasingly secure applications, typical RFID tags are re- quired to expand security features such as data encryption and safe transactions. However, RFID tags have extremely strict low-power consumption requirements. Thus, reduced power consumption and secure data and transactions are a main problem for the next generation RFID tags. Transceiver Smart Buffer Passive Energy Receiver Passive Transceiver Switch Controller Passive Active RFID Tag (PART) System Fig. 1. An architecture of Passive Active RFID Tag This proposed dissertation is placed in the context of an innovative architecture for active RFID tags called Passive Active RFID Tag (PART) shown in Figure 1, which integrates benefits of passive and active RFID tags. It is designed for a low-power, long-range and secure RFID solution [1]. In this dissertation, I propose five contributions studying how to reduce power consumption for passive active RFID tags, how to increase the data security level for RFID commu- nications with the minimum power limitation, and how to profile power consumption of RFID data transactions. Specif- ically, five contributions in this dissertation are (1) designing Smart Buffer circuitry, (2) designing multi-layer securities including Burst Switch encoding/decoding mechanism and Manchester/Differential Manchester coding, (3) developing an Advanced Encryption Standard (AES) with resistance of Differential Power Analysis (DPA), (4) using a power macromodeling model to profile power consumption for RFID encoding techniques and (5) developing a design automation tool to generate an encoding block in hardware. II. SMART BUFFER CIRCUITRY Smart buffer is a hardware-based preprocessor illustrated in Figure 1 which is designed not only for preprocessing RFID packets with low-power dissipation before the RFID controller, but also for being a power management for the controller/processor of passive active RFID tags. The main architecture of smart buffer is depicted in Figure 2....
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