HW 1_Spring2010

HW 1_Spring2010 - clock edge as shown in Fig. 1, where...

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T CLK Q Q_next Figure 1. A T-FF Figure 2. A S-R Latch Q Q_next A B C C B A + + C B A + + A B C C B A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 EEE 333, ASU Spring 2010, David R. Allee Homework #1 Due Thursday, 28 January, submitted to me in class. The objective of this homework is to practice your knowledge of combinational and sequential logic, as well as the implementation with CMOS gates. 1. Boolean Logic DeMorgan’s Law for three variables: C B A C B A = + + Prove the theorem by constructing a truth table for each term: 2. CMOS Implementation Given primary inputs A, B, and C, and 2-input NAND gate only, simplify the following expressions and construct the logic path with the minimum number of gates. (a) ( 29 B B B A + (b) C B A A + (c) A C B A + + 3. Sequential Logic a. A toggle flip-flop has the input T as an enable signal. This FF changes its state at the
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Unformatted text preview: clock edge as shown in Fig. 1, where Q_next is the value of Q at the next cycle. What is the logic function to derive Q_next from T and Q? b. Define the state of this T-FF as the value of Q. Draw the state diagram of a T-FF. c. Fig. 2 shows a Set-Reset latch. Instead of a clock signal, the signals of set (S) and reset (R) control the value of Q. Note that S=R=1 is an illegal set of input, since Q and Q are not complementary under that condition. What is the logic function to derive Q_next from S, R, and Q? d. Define the state of an S-R latch as the value of Q, and the control signal as the legal value of SR. Draw the state diagram of a S-R latch....
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This note was uploaded on 01/28/2010 for the course EEE 333 taught by Professor Ferry during the Spring '09 term at ASU.

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