2-BasicArchitectureAndIO

2-BasicArchitectureAndIO - ECE 485/585 Microprocessor...

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ECE 485/585 Microprocessor System Design Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
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Basic Microcomputer Architecture: I/O
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Basic Architecture and I/O Handouts: Hall •T o p i c s – Simplified Microcomputer Block Diagram –Ba s ic I
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Simplified Microprocessor Architecture Microprocessor Control Data Path [Fetch] [Decode] [Execute]
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Simplified Microcomputer Architecture Microprocessor Memory I/O Device Address, Data, Control Control Data Path [Fetch] [Decode] [Execute] Keyboard Mouse Video display Printer Hard disk drive Floppy Audio card Ethernet WiFi CD R/W DVD
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Memory Addressing • Byte Addressing • Word Addressing – 16-bit half word (Intel: word) – 32-bit word (Intel: doubleword, dword) – 64-bit double word (Intel: quadword, qword) 131 132 133 134 135 136 137 130
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What’s in name? Bytes Intel IA-32 SUN SPARC 2 Word Halfword 4 Doubleword (dword) Word 8 Quadword (qword) Doubleword 16 ------------- Quadword
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Memory Addressing •Two i s su e s – Alignment – Byte order (Big Endian vs. Little Endian) 131 132 133
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Memory Addressing • Alignment – Must words, dword, qwords begin on mod 2, mod 4, mod 8 boundaries? 131 132 133 134 135 136 137 130 131 132 133 134 135 136 137 130 131 132 133 134 135 136 137 130
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Memory Addressing • Alignment – Or are there no alignment restrictions? 131 132 133 134 135 136 137 130 131 132 133 134 135 136 137 130 131 132 133 134 135 136 137 130
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Alignment: Why Care? – Non-aligned memory references may cause multiple memory accesses – Consider a system in which memory reads return 4 bytes and a reference to a word spans a 4-byte boundary: two memory access are required – Complicates memory and cache controller design – Even in systems with no alignment restrictions, assemblers typically have directives to force alignment for efficiency 131 132 133 134 135 136 137 130
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Memory Addressing • Byte order: Little Endian 131 132 133 134 135 136 137 130 byte 0 byte 1 MSB LSB 131 130 word byte 6 byte 7 MSB LSB byte 4 byte 5 byte 2 byte 3 byte 0 byte 1 137 136 135 134 133 132 131 130 quadword
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Memory Addressing • Little Endian with no Alignment Restrictions 131 132 133 134 135 136 137 130 byte 0 byte 1 MSB LSB Byte at location 133 could be high order byte of word located at location 132 or low order byte of word located at location 133 133 132 byte 0 byte 1 MSB LSB 134 133
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Memory Addressing • Byte order: Big Endian 131 132 133 134 135 136 137 130 byte 0 byte 1 MSB LSB 130 131 word byte 6 byte 7 MSB LSB byte 4 byte 5 byte 2 byte 3 byte 0 byte 1 130 131 132 133 134 135 136 137 quadword
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Actual Systems • Pros/Cons – Often exaggerated – Little Endian • Character strings will appear “backwards” in registers
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This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

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2-BasicArchitectureAndIO - ECE 485/585 Microprocessor...

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