3b-Buses - ECE 485/585 Microprocessor System Design Prof....

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ECE 485/585 Microprocessor System Design Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
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Serial Buses and USB
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Bus Trends • Parallel to Serial • Lower Voltage – Can’t accomplish large voltage swings at high speed – Power consumption • Differential Signaling • Clock Forwarding and Clock Embedding •E n c o d i n g –NRZ I – 8b/10b
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Why Serial? “Parallel” “Serial” Device A Device B + - + - Device A Device B 10 bidirectional wires at 250Mbps pair unidirectional wires at 2500Mbps (2.5Gbps)
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Traditional Parallel Bus Device A Device B Used in low to medium 100 MHz range •I s s u e s – Board trace length mismatch effect on skew – Clock skew across devices – Faster data rate squeezes “eye”
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Source Synchronous Bus Device A Device B Used in 200MHz to 1.6GHz range Clock signal is “forwarded” with data Design impact: – Board layout track length mismatch still adds to skew – Eliminates skew error term caused by clock domain skew – Allows faster cycle times than parallel
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Source Synchronous - Clock Forward Clock Data 1 Data 2 Data 3 Data 4 Clock is transmitted continuously from Tx to Rx Removes clock distribution skew Examples – HyperTransport – Parallel RapidIO
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Source Synchronous - Latch Forward Latch Data 1 Data 2 Data 3 Data 4 • Latch assertion is transmitted when valid data is present •Ex amp l e s – Bi-directional buses – Memory Interfacing (e.g. DDR)
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Embedded Clock Data Clock Clock signal embedded with data Clock signal is embedded with data – Edge density guaranteed by encoding scheme •Ex amp l e s – PCI Express –USB –Ser ia l Rap idIO – Infiniband
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SerDes (Serial/Deserializer) Tx Serialize 10 x 250Mbps Low Speed Parallel Data 1 x 2.5Gbps High Speed Serial Data Deserialize Rx
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Differential Signaling Differential, point to point Complementary signals transmitted Receiver detects voltage difference between lines Low amplitudes (200mV - 400mV typical), high speeds Good noise immunity Pair routed together – noise cancels out LVDS – Low Voltage Differential Signaling ANSI/TIA/EIA 644-1995 standard (signaling only, not protocol or connectors) 3.125 Gbps, +/- 350mV “Gbps at mWs” -- High speed & low power consumption FibreChannel, Gigabit Ethernet, HDMI, DVI May be edge-based!
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SerDes - Parallel and Serial Conversion R e g i s t r Serializer TxP XmitClk SysClk 10-bit Parallel Interface TxN Clock Recovery and Data Deserializer RxP Rx Parallel Interface 10-bit RxN Recovered Clock
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Edge Lock Technique (Tracking Receiver) Device A Device A sends pulse train to Device B Device B Device B “locks” onto edges to be in sync with pulse stream
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8b/10b Transmission Code TX FIFO 8B/10B Encoder Serializer RX FIFO 8B/10B Decoder Deserializer Parallel Data RX FIFO 8B/10B Decoder Deserializer Parallel Data TX FIFO 8B/10B Encoder Serializer Parallel Data Parallel Data + _ + _ Device A Device B Developed by IBM in 1983
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This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

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3b-Buses - ECE 485/585 Microprocessor System Design Prof....

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