5-Memory - ECE 485/585 Microprocessor System Design Prof....

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ECE 485/585 Microprocessor System Design Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
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Memory • Memory Hierarchy • Taxonomy of Memories •SRAM – Basic Cell, Devices, Timing • Memory Organization – Multiple banks, interleaving •DRAM – Basic Cell, Timing – DRAM Evolution • Error Correction "640K ought to be enough for anybody." -- Bill Gates, 1981
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Memory Taxonomy Read/Write Memory Non-Volatile Volatile Read Only Random Access Non-Random Access SRAM DRAM Shift Register FIFO CAM EPROM E 2 PROM Flash NAND NOR NVRAM Mask ROM PROM
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Computer Memory Hierarchy Control Datapath Secondary Storage (Disk) Processor Registers Main Memory (DRAM) Second Level Cache (SRAM) On-C hip Ca che Tertiary Storage (Tape) Third Level Cache (SRAM) I n c r e a s i g S z , D p d C o t / G B Intermediate results Archive Backup Instructions Data [Cached Files] File System Paging Cached DRAM From Hennessy & Patterson, Computer Architecture: A Quantitative Approach (4 th edition)
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Register Files • General Purpose Registers • Multiple Ports – Support CPU architecture’s datapaths • Ability to read two operands, write one • Operate at CPU speed data a data b data c Register File sel a sel b sel c
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Register File Internals For read operations, the regfile is equivalent to a 2-D array of flip-flops with tri-state outputs For write operations, we add some additional circuitry How do we get from “RegID" to "SELi"?
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Address Decoding Address decoder generates a one-hot code (1-of-n code) from the address binary to unary The output is used for row selection
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Accessing Register Files Read – “Address following” • Change address – Data from new address appears on output • Asynchronous Write is synchronous If WE, input data is written to selected word on the clock edge Clock RegID WE Din Dout Register File RegID Dout Din WE RegID X R[X] RegID Y R[Y] val Clock val
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SRAM Technology Write Write bit and bit onto bit lines Select desired word (“row”) Turns on pass transistors Writes new value to cell [One inverter input will be low, turning its output high] Read Select desired word (“row”) One bit line will be pulled low Other will remain high Takes long time for bit line to be pulled low with tiny transistor Don’t need to wait – can just sense difference between two bit lines! word line bit line bit line addr data SRAM Cell 6 transistors Which will be longer: bit lines or word lines? Bit lines! For density and low power, want tiny transistors Unable to drive long bit lines Pre-charge bit lines (Vdd/2) before read Use differential between bit and bit
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Dual-ported Memory Internals Add decoder, another set of read/write logic, bits lines, word lines Example cell: SRAM Repeat everything but cross- coupled inverters.
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This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

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5-Memory - ECE 485/585 Microprocessor System Design Prof....

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