6-CachesII - ECE 485/585 Microprocessor System Design Prof....

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ECE 485/585 Microprocessor System Design Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
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ectures Lectures Handouts: none • Topics – Caches easuring and Improving Cache Performance • Measuring and Improving Cache Performance
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easuring Cache Performance Measuring Cache Performance •A v e r a ge Memory Access Time (AMAT) = (Hit Rate x Hit Time) + (Miss Rate x Miss Time) • CPU Execution Time (CPU clock cycles + Memory stall cycles) x Clock Period = (CPU clock cycles + Memory stall cycles) x Clock Period • Memory stall cycles = Number of misses x Miss penalty = IC x misses/instruction x Miss penalty = IC x memory access/instruction x Miss rate x Miss penalty IC = instruction count
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proving Cache Performance Improving Cache Performance hree Options Three Options – Reduce Miss Rate l i i • Larger line size • Larger cache size igher associativity Higher associativity – Reduce Miss Penalty ultilevel caches Multilevel caches • Prioritizing reads over writes – Reduce Hit Time • Avoiding address translation when indexing cache
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educe Miss Rate Reduce Miss Rate • Increase size of cache Æ increase hit time, power crease associativity • Increase associativity Æ increase hit time • Increase size of cache line Æ Trade-offs!! Æ increase miss penalty • Victim cache l l f l l i t i hf l d l i – Small fully associative cache of replaced lines • Hardware pre-fetch – If available memory bandwidth
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onflict Capacity Cache Size 0.14 1-way Conflict, Capacity, Cache Size 0.1 0.12 2-way 4-way Conflict 04 0.06 0.08 8-way Capacity Miss Rate 0 0.02 0.04 Cache Size (KB) 1 2 4 8 16 32 64 128 Compulsory
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erformance
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This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

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6-CachesII - ECE 485/585 Microprocessor System Design Prof....

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