6-CachesIII - ECE 485/585 Microprocessor System Design Prof...

Info iconThis preview shows pages 1–14. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 485/585 Microprocessor System Design Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lecture Handouts: •T o p i c s –C a c h e s • Cache Coherence – Single processors, multiple masters – Symmetric multiprocessors • Snooping Protocols for Cache Coherence • Intel Cache Evolution
Background image of page 2
Cache Coherence • Normal operation may permit an item to be “stale” – Cache/memory • Needed in case of Write Back caches • Dirty bit suffices – L1/L2/L3 Caches • “Inclusivity” if next level caches are a superset of lower level caches •L i cache needs to notify L i-1 cache when victim removed from cache – Single processors with multiple bus masters •e . g . DMA – Multiple processors sharing memory, but with own caches • How do we ensure that the cache is “coherent”?
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Shared Memory Multiprocessor
Background image of page 4
The Problem
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
The Problem
Background image of page 6
The Solution • All processors “snoop” on memory transactions • Processors signal if they have a cached copy • All processors implement same cache coherence policy • Several variations in use – MEI, MESI, MOESI • Most modern processors employ one of these – Intel Pentium, AMD, SunSparc, PowerPC • MESI (Intel Pentium, PowerPC) – Modified/Exclusive/Shared/Invalid – 4 states for each cache line (instead of 2)
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Shared Memory Multiprocessor HIT# -- Snooping processor indicates it has copy in its cache (open drain, shared line) HITM# -- Snooping processor indicates it has copy in its cache and it’s been modified (open drain, shared line) Memory Controller also sees HIT#, HITM# (so it won’t service a read request since valid data is held not in memory but in a cache which needs to be written back to memory first).
Background image of page 8
MESI Protocol
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MESI Protocol
Background image of page 10
MESI Protocol
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
MESI (Write Back Cache) • Modified – The cached copy is the only valid copy of the line – No other processor caches contain the line – The memory copy is out of date • Exclusive – No other processor has a copy of the cached item – The processor’s cache and memory are identical •S h a r e d – At least one other processor has a copy of the line – The cached copies and memory are identical •I n v a l i d – The cache entry is invalid (doesn’t hold a copy of the line)
Background image of page 12
CPU Write • Cached item (Shared/Exclusive/Modified) – Employ Write Policy • Write Through
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 14
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

Page1 / 50

6-CachesIII - ECE 485/585 Microprocessor System Design Prof...

This preview shows document pages 1 - 14. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online