7-FSB - ECE 485/585 Microprocessor System Design Prof Mark G Faust Maseeh College of Engineering and Computer Science Lecture Handouts Topics Intel

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ECE 485/585 Microprocessor System Design Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
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Lecture Handouts: •Top i c s – Intel Front Side Bus (FSB) • Motivation – Performance – Wider Access
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Line Size Evolution Processor Line Size 486 16 bytes Pentium P6 Family 32 bytes Pentium 4, Xeon 128 bytes Pentium M 64 bytes
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IA32 Memory Access • Evolution towards larger physical address spaces –16 Æ 32 Æ 36 • Wider data buses (64 bits) • Quad-word aligned memory accesses • Burst mode memory reads – Faster cache line fill, less overhead
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Typical Multiprocessor Pentium System Front Side Bus
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Quad word aligned access Pentium: 2 36 (64 GB) physical address space Address quadword at a time (8 bytes) Don’t need lower 3 address bits Need to specify which byte(s) interested in BE[7:0] (Byte Enables) Consider a reference to a mis-aligned quadword e.g. 8 bytes beginning at location 134 Two quadword memory references Consider a reference to a mis-aligned word e.g. 2 bytes beginning at location 137 Two quadword memory references 131 132 133 134 135 136 137 130
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FSB Agent Types • Request – Transaction initiator (memory or I/O read/write) – Example: CPU – Example: MCH (North Bridge) on behalf of I/O device • Response – Target of transaction (I/O or memory) – Example: Memory controller is “response only” agent • Snoop – Any device with a cache (typically processor)
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This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

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7-FSB - ECE 485/585 Microprocessor System Design Prof Mark G Faust Maseeh College of Engineering and Computer Science Lecture Handouts Topics Intel

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