8-MultitaskingPaging

8-MultitaskingPaging - ECE 485/585 Microprocessor System Design Prof Mark G Faust Maseeh College of Engineering and Computer Science Virtual Memory

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ECE 485/585 Microprocessor System Design Prof. Mark G. Faust Maseeh College of Engineering and Computer Science
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Virtual Memory
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Origins of Virtual Memory Early days of computing (pre-1960) Physical memory too small to accommodate entire user program Programs partitioned into segments which were overlayed in physical memory (to/from disk) User program Physical memory segment A A B segment B Done manually by programmer Tedious and very difficult to do optimally to minimize swapping of overlays
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Virtual Addressing Early 1960s… CPU Physical address Physical addressing memory CPU Virtual addressing memory Physical address MMU memory management unit Virtual address Address translation Mapping from virtual to physical addresses Virtual address space could be larger than physical address space Each process could have its own virtual address space
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Segmentation Address is (Segment, Offset) pair Each segment has own contiguous address space Facilitates relocating code Segment can be relocated anywhere in physical memory position independent code! Offsets in segment maintained Physical address is Base Address of Segment + Offset User program segment A (A,2) segment B 0 1 2 Physical memory A Base Address Segment A 0 1 2
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Segmentation segment offset Virtual Address Segment Table Base address Base address Base address Base address Base address Base address + Physical Address
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Segmentation: Intel Code and data references Segment:Offset e.g. CS:IP Segment registers Contain base address of segment Code Segment (CS) Default Data Segment (DS) Stack Segment (SS) Additional Data Segments Simplest case (e.g. Real Mode) Linear Address = Segment Base (shifted) + Offset
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Real Mode Segmentation Default Data Segment Register (DS) Contents shifted left 4 to form base address Creates effective 20 bit base address Offset (actual operand) Added to shifted base address to form linear address Same process occurs for Normal instruction execution Code Segment (CS) Stack operations Stack segment (SS) Explicit segment references allowed “Segment overrides” MOV BH, ES:[0002]
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Segment-Level Protection Segmentation evolved to provide additional support – Protect OS and other processes from each other • Malicious process • Buggy process – Aid to debugging • Process memory image not corrupted • Debugger resident and not corrupted Every memory reference is checked – Type Check (e.g. don’t write to code segment) – Limit Check (e.g. offset within segment’s range) – Restriction of addressable domain (through segments) – Restriction of procedure entry points (can’t jump/branch to random places in other segments – e.g. system code!) – Restriction of instruction set (only OS can manipulate segment registers, etc)
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Segment-Level Protection • Restriction of instruction set – Reserved to Operating System (Level 0) •HLT H a l t • INVD
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This note was uploaded on 02/01/2010 for the course ECE 585 taught by Professor Faust during the Fall '08 term at Portland State.

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8-MultitaskingPaging - ECE 485/585 Microprocessor System Design Prof Mark G Faust Maseeh College of Engineering and Computer Science Virtual Memory

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