ECE 485/585 Fall 2009 Homework 2 1. Use an on-line article index from the PSU library or another library of your choice to obtain and read a copy of the article by David A. Patterson, “Latency Lags Bandwidth”, Communications of the ACM , 47:10, October 2004, 71-75. 2. Consider two SRAMs. One is 256Kx4 and has a tRC of 8 ns (125 MHz). The other is 64Kx16 and has a tRC of 10ns (100 MHz). What are the effective bandwidths (in MB/s) of the two devices? 3. Now, consider that the devices are to be used to provide data to a 32-bit bus. What is the data rate that can be sustained on the bus if it is driven by eight of the 256Kx4 chips in parallel? 4. What is the corresponding bus data rate if two of the 64Kx16 SRAMs are used in parallel? 5. Ignoring control, power, and ground pins, discuss the trade-offs in pin count between a 1Mbit SRAM configured as a 1Mx1 device or a 64Kx16 device. Assume bidirectional data pins. 6.
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